linux-stable.git/drivers/clk, branch v4.1.41

clk: qcom: msm8916: Fix crypto clock flags

2016-07-11T03:07:26+00:00

[ Upstream commit 2a0974aa1a0b40a92387ea03dbfeacfbc9ba182c ]

This patch adds the CLK_SET_RATE_PARENT flag for the crypto core and
ahb blocks.  Without this flag, clk_set_rate can fail for certain
frequency requests.

Signed-off-by: Andy Gross 
Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: qcom: msm8960: Fix ce3_src register offset

2016-07-11T03:07:18+00:00

[ Upstream commit 0f75e1a370fd843c9e508fc1ccf0662833034827 ]

The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.

Tested-by: Srinivas Kandagatla 
Tested-by: Bjorn Andersson 
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: versatile: sp810: support reentrance

2016-07-11T03:07:17+00:00

[ Upstream commit ec7957a6aa0aaf981fb8356dc47a2cdd01cde03c ]

Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.

Rename the timclken<0> .. timclken to sp810__
so every clock on every instance gets a unique name.

This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:

------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
  clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[] (unwind_backtrace) from []
             (show_stack+0x10/0x14)
[] (show_stack) from []
             (dump_stack+0x84/0x9c)
[] (dump_stack) from []
             (warn_slowpath_common+0x74/0xb0)
[] (warn_slowpath_common) from []
             (warn_slowpath_null+0x1c/0x24)
[] (warn_slowpath_null) from []
             (clk_sp810_of_setup+0x110/0x154)
[] (clk_sp810_of_setup) from []
             (of_clk_init+0x12c/0x1c8)
[] (of_clk_init) from []
             (time_init+0x20/0x2c)
[] (time_init) from []
             (start_kernel+0x244/0x3c4)
[] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---

Cc: Michael Turquette 
Cc: Pawel Moll 
Fixes: 6e973d2c4385 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: qcom: msm8960: fix ce3_core clk enable register

2016-07-11T03:07:17+00:00

[ Upstream commit 732d6913691848db9fabaa6a25b4d6fad10ddccf ]

This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla 
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: rockchip: free memory in error cases when registering clock branches

2016-07-11T03:07:17+00:00

[ Upstream commit 2467b6745e0ae9c6cdccff24c4cceeb14b1cce3f ]

Add free memeory if rockchip_clk_register_branch fails.

Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure...")
Signed-off-by: Shawn Lin 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

clk: rockchip: initialize flags of clk_init_data in mmc-phase clock

2016-07-11T00:19:51+00:00

[ Upstream commit 595144c1141c951a3c6bb9004ae6a2bc29aad66f ]

The flags element of clk_init_data was never initialized for mmc-
phase-clocks resulting in the element containing a random value
and thus possibly enabling unwanted clock flags.

Fixes: 89bf26cbc1a0 ("clk: rockchip: Add support for the mmc clock phases using the framework")
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocks

2016-04-18T12:50:33+00:00

[ Upstream commit e8b63288b37dbb8457b510c9d96f6006da4653f6 ]

hclk_cpubus needs to keep running because it is needed for devices like
the rom, i2s0 or spdif to be accessible via cpu. Without that all
accesses to devices (readl/writel) return wrong data. So add it
to the list of critical clocks.

Fixes: 78eaf6095cc763c ("clk: rockchip: disable unused clocks")
Signed-off-by: Alexander Kochetkov 
Cc: stable@vger.kernel.org # 4.1.x-
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188

2016-04-18T12:50:33+00:00

[ Upstream commit 3bba75a2ec32bd5fa7024a4de3b8cf9ee113a76a ]

Now that the rockchip clock subsystem does clock gating with GPIO banks,
these are no longer enabled once during probe and no longer stay enabled
for eternity. When all these clocks are disabled, the parent clock pclk_peri
might be disabled too, as no other child claims it. So, we need to add pclk_peri
to the critical clocks.

Signed-off-by: Romain Perier 
Tested-by: Michael Niewoehner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: rockchip: add pclk_cpu to the list of rk3188 critical clocks

2016-04-18T12:50:32+00:00

[ Upstream commit 1166160ab531198f7abc773992c0e04d0f9b7600 ]

pclk_cpu needs to keep running because it is needed for devices like
the act8865 regulator but with the recent gpio clock handling this is
not always the case anymore. So add it to the list of critical clocks.

Signed-off-by: Michael Niewoehner 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: versatile-icst: fix memory leak

2015-12-09T19:03:20+00:00

commit 7bdccef34fc67d3fce6778a018601dd41e43c5ce upstream.

A static code checker found a memory leak in the Versatile
ICST code. Fix it.

Fixes: a183da637c52 "clk: versatile: respect parent rate in ICST clock"
Reported-by: Stephen Boyd 
Signed-off-by: Linus Walleij 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman