linux-stable.git/drivers/clk, branch v3.18.4

clk: at91: keep slow clk enabled to prevent system hang

2015-01-27T16:29:38+00:00

commit dca1a4b5ff6e2c25adeff366eb06270dadeab3db upstream.

All slow clk users are not properly claiming it (get + prepare + enable)
before using it.
If all users properly claiming this clock release it, the clock is
disabled, but faulty users still depends on it, and the system hangs.

This fix prevents the slow clock from being disabled, and should solve the
hanging issue, but offending drivers should be patched to properly claim
this clock.

Signed-off-by: Boris Brezillon 
Reported-by: Bo Shen 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: berlin: bg2q: remove non-exist "smemc" gate clock

2015-01-27T16:29:38+00:00

commit b71e8ecd57c8aae5b1815782c47b74ffe3efc09a upstream.

The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
register is for nfc. Current code use bit19 for non-exist "smemc"
incorrectly, this prevents eMMC from working due to the sdhci's
"core" clk is still gated.

Signed-off-by: Jisheng Zhang 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: fix rk3066 pll lock bit location

2015-01-27T16:29:38+00:00

commit 12551f0239b50c88352e3292dd7703382addbf5e upstream.

The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.

The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.

Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.

Signed-off-by: Heiko Stuebner 
Fixes: 2c14736c75db ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: FUKAUMI Naoki 
Signed-off-by: Greg Kroah-Hartman

clk: rockchip: fix rk3288 cpuclk core dividers

2015-01-27T16:29:38+00:00

commit 9880d4277f6aab6b21404c824f9d9c652ba518ac upstream.

Commit 0e5bdb3f9fa5 (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.

Reported-by: Sonny Rao 
Fixes: 0e5bdb3f9fa5 ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: Heiko Stuebner 
Reviewed-by: Doug Anderson 
Signed-off-by: Greg Kroah-Hartman

Revert "clk: ppc-corenet: Fix Section mismatch warning"

2015-01-27T16:29:38+00:00

commit 176a107b868781c8d6868454aea7d07e0b82d6b8 upstream.

This reverts commit da788acb28386aa896224e784954bb73c99ff26c.

That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the memories occupied by this struct
after boot while this driver is still registered in the driver core.
The kernel would panic when accessing this driver struct.

Signed-off-by: Kevin Hao 
Acked-by: Scott Wood 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: Don't try to use a struct clk* after it could have been freed

2015-01-27T16:29:38+00:00

commit 10cdfe54dab034311c8e2fad9ba2dffbe616caa9 upstream.

As __clk_release could call kfree on clk and then we wouldn't have a safe way
of getting the module that owns the clock.

Signed-off-by: Tomeu Vizoso 
Fixes: fcb0ee6a3d33 ("clk: Implement clk_unregister")
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: Really fix deadlock with mmap_sem

2015-01-27T16:29:38+00:00

commit 89f7e9de59bf3e3cda2e00de12c66db22675a7cf upstream.

Commit 6314b6796e3c (clk: Don't hold prepare_lock across debugfs
creation, 2014-09-04) forgot to update one place where we hold
the prepare_lock while creating debugfs directories. This means
we still have the chance of a deadlock that the commit was trying
to fix. Actually fix it by moving the debugfs creation outside
the prepare_lock.

Reported-by: Russell King 
Fixes: 6314b6796e3c "clk: Don't hold prepare_lock across debugfs creation"
Signed-off-by: Stephen Boyd 
Reviewed-by: Thomas Gleixner 
Signed-off-by: Michael Turquette 
[mturquette@linaro.org: removed lockdep_assert]
Signed-off-by: Greg Kroah-Hartman

clk: samsung: Fix double add of syscore ops after driver rebind

2015-01-27T16:29:38+00:00

commit c31844ffdbd4e73a16c66e9d7df8ec290ab4b159 upstream.

During driver unbind the syscore ops were not unregistered which lead to
double add on syscore list:

$ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/unbind
$ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/bind
[ 1463.044061] ------------[ cut here ]------------
[ 1463.047255] WARNING: CPU: 0 PID: 1 at lib/list_debug.c:36 __list_add+0x8c/0xc0()
[ 1463.054613] list_add double add: new=c06e52c0, prev=c06e52c0, next=c06d5f84.
[ 1463.061625] Modules linked in:
[ 1463.064623] CPU: 0 PID: 1 Comm: bash Tainted: G        W      3.18.0-rc5-next-20141121-00005-ga8fab06eab42-dirty #1022
[ 1463.075338] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[ 1463.083046] [] (show_stack) from [] (dump_stack+0x70/0xbc)
[ 1463.090236] [] (dump_stack) from [] (warn_slowpath_common+0x74/0xb0)
[ 1463.098295] [] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
[ 1463.106962] [] (warn_slowpath_fmt) from [] (__list_add+0x8c/0xc0)
[ 1463.114760] [] (__list_add) from [] (register_syscore_ops+0x30/0x3c)
[ 1463.122819] [] (register_syscore_ops) from [] (exynos_audss_clk_probe+0x36c/0x460)
[ 1463.132091] [] (exynos_audss_clk_probe) from [] (platform_drv_probe+0x48/0xa4)
[ 1463.141013] [] (platform_drv_probe) from [] (driver_probe_device+0x13c/0x37c)
[ 1463.149852] [] (driver_probe_device) from [] (bind_store+0x90/0xe0)
[ 1463.157822] [] (bind_store) from [] (drv_attr_store+0x20/0x2c)
[ 1463.165363] [] (drv_attr_store) from [] (sysfs_kf_write+0x4c/0x50)
[ 1463.173252] [] (sysfs_kf_write) from [] (kernfs_fop_write+0xbc/0x198)
[ 1463.181395] [] (kernfs_fop_write) from [] (vfs_write+0xa0/0x1a8)
[ 1463.189104] [] (vfs_write) from [] (SyS_write+0x40/0x8c)
[ 1463.196122] [] (SyS_write) from [] (ret_fast_syscall+0x0/0x48)
[ 1463.203655] ---[ end trace 08f6710c9bc8d8f3 ]---
[ 1463.208244] exynos-audss-clk 3810000.audss-clock-controller: setup completed

Signed-off-by: Krzysztof Kozlowski 
Fixes: 1241ef94ccc3 ("clk: samsung: register audio subsystem clocks using common clock framework")
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Greg Kroah-Hartman

clk: pxa: fix pxa27x CCCR bit usage

2014-11-17T19:25:29+00:00

Trivial fix to check the A bit of CCCR for memory frequency
calculations, where the shift of the bit index was missing, triggering a
wrong calculation of memory frequency.

Signed-off-by: Robert Jarzmik 
Signed-off-by: Michael Turquette

clk-divider: Fix READ_ONLY when divider > 1

2014-11-17T19:13:52+00:00

Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
recalc_rate() and round_rate() clock callbacks to be omitted.

However using this flag has the unfortunate side effect of causing the
clock recalculation code when a clock rate change is attempted to always
treat it as a pass-through clock, i.e. with a fixed divide of 1, which
may not be the case. Child clock rates are then recalculated using the
wrong parent rate.

Therefore instead of dropping the recalc_rate() and round_rate()
callbacks, alter clk_divider_bestdiv() to always report the current
divider as the best divider so that it is never altered.

For me the read only clock was the system clock, which divided the PLL
rate by 2, from which both the UART and the SPI clocks were divided.
Initial setting of the UART rate set it correctly, but when the SPI
clock was set, the other child clocks were miscalculated. The UART clock
was recalculated using the PLL rate as the parent rate, resulting in a
UART new_rate of double what it should be, and a UART which spewed forth
garbage when the rate changes were propagated.

Signed-off-by: James Hogan 
Cc: Thomas Abraham 
Cc: Tomasz Figa 
Cc: Max Schwarz 
Cc:  # v3.16+
Acked-by: Haojian Zhuang 
Signed-off-by: Michael Turquette