linux-stable.git/drivers/clk, branch v3.18.35

clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188

2016-04-18T12:49:15+00:00

[ Upstream commit 3bba75a2ec32bd5fa7024a4de3b8cf9ee113a76a ]

Now that the rockchip clock subsystem does clock gating with GPIO banks,
these are no longer enabled once during probe and no longer stay enabled
for eternity. When all these clocks are disabled, the parent clock pclk_peri
might be disabled too, as no other child claims it. So, we need to add pclk_peri
to the critical clocks.

Signed-off-by: Romain Perier 
Tested-by: Michael Niewoehner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: rockchip: add pclk_cpu to the list of rk3188 critical clocks

2016-04-18T12:49:15+00:00

[ Upstream commit 1166160ab531198f7abc773992c0e04d0f9b7600 ]

pclk_cpu needs to keep running because it is needed for devices like
the act8865 regulator but with the recent gpio clock handling this is
not always the case anymore. So add it to the list of critical clocks.

Signed-off-by: Michael Niewoehner 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: versatile: off by one in clk_sp810_timerclken_of_get()

2015-10-28T02:14:38+00:00

[ Upstream commit 3294bee87091be5f179474f6c39d1d87769635e2 ]

The ">" should be ">=" or we end up reading beyond the end of the array.

Fixes: 6e973d2c4385 ('clk: vexpress: Add separate SP810 driver')
Signed-off-by: Dan Carpenter 
Acked-by: Pawel Moll 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: ti: fix dual-registration of uart4_ick

2015-10-28T02:14:26+00:00

[ Upstream commit 19e79687de22f23bcfb5e79cce3daba20af228d1 ]

On the OMAP AM3517 platform the uart4_ick gets registered
twice, causing any power management to /dev/ttyO3 to fail
when trying to wake the device up.

This solves the following oops:

[] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008
[] PC is at serial_omap_pm+0x48/0x15c
[] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c

Fixes: aafd900cab87 ("CLK: TI: add omap3 clock init file")
Cc: stable@vger.kernel.org
Cc: mturquette@baylibre.com
Cc: sboyd@codeaurora.org
Cc: linux-clk@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-kernel@lists.codethink.co.uk
Signed-off-by: Ben Dooks 
Signed-off-by: Tero Kristo 
Signed-off-by: Sasha Levin

clk: keystone: add support for post divider register for main pll

2015-08-22T18:05:31+00:00

[ Upstream commit 02fdfd708fd252a778709beb6c65d5e7360341ac ]

Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.

Signed-off-by: Murali Karicheri 
Signed-off-by: Michael Turquette 
Signed-off-by: Sasha Levin

clk: at91: fix h32mx prototype inclusion in pmc header

2015-07-01T19:37:14+00:00

[ Upstream commit 28df9c2fb6f896179fcffd5a3f5a86e2d1dff0a5 ]

Trivial fix that prevents to compile this pmc clock driver if h32mx clock is
present but smd clock isn't.

Signed-off-by: Nicolas Ferre 
Signed-off-by: Boris Brezillon 
Acked-by: Alexandre Belloni 
Fixes: bcc5fd49a0fd ("clk: at91: add a driver for the h32mx clock")
Cc:  # 3.18+
Signed-off-by: Sasha Levin

clk: at91: pll: fix input range validity check

2015-07-01T19:36:18+00:00

[ Upstream commit 6c7b03e1aef2e92176435f4fa562cc483422d20f ]

The PLL impose a certain input range to work correctly, but it appears that
this input range does not apply on the input clock (or parent clock) but
on the input clock after it has passed the PLL divisor.
Fix the implementation accordingly.

Cc:  # v3.14+
Signed-off-by: Boris Brezillon 
Reported-by: Jonas Andersson 
Signed-off-by: Sasha Levin

clk: at91: usb: fix determine_rate prototype

2015-05-17T23:12:33+00:00

Commit c67881fc890916206e723329e774391c6ed354ce is a backport of
0b67c43ce36a9964f1d5e3f973ee19eefd3f9f8f upstream commit, fixing a
bug on clk rate change propagation.
But in 4.0 ->determine_rate() prototype has changed, thus introducing
a prototype mismatch when applying it on 3.19.

Signed-off-by: Boris Brezillon 
Signed-off-by: Sasha Levin

clk: qcom: fix RCG M/N counter configuration

2015-05-17T23:12:19+00:00

[ Upstream commit 0b21503dbbfa669dbd847b33578d4041513cddb2 ]

Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.

Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.

Signed-off-by: Archit Taneja 
Fixes: bcd61c0f535a (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd 

Signed-off-by: Sasha Levin

clk: qcom: Fix i2c frequency table

2015-05-17T23:12:19+00:00

[ Upstream commit 0bf0ff82c34da02ee5795101b328225a2d519594 ]

PXO is 25MHz, not 27MHz. Fix the table.

Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global
clock controller (GCC)"

Signed-off-by: Stephen Boyd 
Reviewed-by: Andy Gross 
Tested-by: Andy Gross 
Signed-off-by: Michael Turquette 
Signed-off-by: Sasha Levin