linux-stable.git/drivers/clk, branch v3.16.57

clk: ti: dra7-atl-clock: fix child-node lookups

2018-02-13T18:42:22+00:00

commit 33ec6dbc5a02677509d97fe36cd2105753f0f0ea upstream.

Fix child node-lookup during probe, which ended up searching the whole
device tree depth-first starting at parent rather than just matching on
its children.

Note that the original premature free of the parent node has already
been fixed separately, but that fix was apparently never backported to
stable.

Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Fixes: 660e15519399 ("clk: ti: dra7-atl-clock: Fix of_node reference counting")
Cc: Peter Ujfalusi 
Signed-off-by: Johan Hovold 
Acked-by: Peter Ujfalusi 
Signed-off-by: Stephen Boyd 
Signed-off-by: Ben Hutchings

clk: ti: dra7-atl-clock: Fix of_node reference counting

2018-02-13T18:42:22+00:00

commit 660e1551939931657808d47838a3f443c0e83fd0 upstream.

of_find_node_by_name() will call of_node_put() on the node so we need to
get it first to avoid warnings.
The cfg_node needs to be put after we have finished processing the
properties.

Signed-off-by: Peter Ujfalusi 
Tested-by: Nishanth Menon 
Signed-off-by: Stephen Boyd 
Signed-off-by: Ben Hutchings

clk: tegra: Fix cclk_lp divisor register

2018-02-13T18:42:13+00:00

commit 54eff2264d3e9fd7e3987de1d7eba1d3581c631e upstream.

According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław 
Acked-By: Peter De Schrijver 
Signed-off-by: Thierry Reding 
Signed-off-by: Ben Hutchings

clk/efm32gg: fix dt init prototype

2017-11-11T13:33:46+00:00

commit 8ce8ebeb572d70e672a8d158e93ffaac80ea7576 upstream.

Since commit 54196ccbe0ba (of: consolidate linker section OF match table
declarations) which went into 3.16-rc1 the following compiler warning is
generated:

	In file included from drivers/clk/clk-efm32gg.c:12:0: include/linux/of.h:772:20:
	warning: comparison of distinct pointer types lacks a cast [enabled by default]
		.data = (fn == (fn_type)NULL) ? fn : fn  }
			    ^
	include/linux/of.h:785:3: note: in expansion of macro '_OF_DECLARE'
	   _OF_DECLARE(table, name, compat, fn, of_init_fn_1)
	   ^
	include/linux/clk-provider.h:545:42: note: in expansion of macro 'OF_DECLARE_1'
	 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
						  ^
	drivers/clk/clk-efm32gg.c:81:1: note: in expansion of macro 'CLK_OF_DECLARE'
	 CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
	 ^

Fix it by making efm32gg_cmu_init return void.

Cc: Rob Herring 
Reported-by: Bryan Hundven 
Reviewed-by: Arnd Bergmann 
Signed-off-by: Uwe Kleine-König 
Signed-off-by: Mike Turquette 
Signed-off-by: Arnd Bergmann 
Signed-off-by: Ben Hutchings

clk: renesas: mstp: ensure register writes complete

2017-06-05T20:17:10+00:00

commit f59de563358eb9351b7f8f0ba2d3be2ebb70b93d upstream.

When there is no status bit, it is possible for the clock enable/disable
operation to have not completed by the time the driver code resumes
execution. This is due to the fact that write operations are sometimes
queued and delayed internally. Doing a read ensures the write operations
has completed.

Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Stephen Boyd 
[bwh: Backported to 3.16:
 - Use barrier() instead of barrier_data()
 - Adjust filename]
Signed-off-by: Ben Hutchings

clk: samsung: mark s3c...._clk_sleep_init() as __init

2017-06-05T20:16:59+00:00

commit 02c952c8f95fd0adf1835704db95215f57cfc8e6 upstream.

These functions are referencing s3c...._clk_regs[], which are marked as
__initdata. When compiling with CONFIG_DEBUG_SECTION_MISMATCH=y, this
produces warnings like

WARNING: vmlinux.o(.text+0x198350):
Section mismatch in reference from the function s3c2410_clk_sleep_init()
to the (unknown reference) .init.data:(unknown)

Mark the s3c...._clk_sleep_init() functions as __init in
order to fix this.

Fixes: ca2e90ac1809 ("clk: samsung: add clock controller driver for s3c2412")
Signed-off-by: Martin Kaiser 
Reviewed-by: Chanwoo Choi 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Sylwester Nawrocki 
Signed-off-by: Ben Hutchings

clk: hisilicon: fix lock assignment

2017-06-05T20:16:59+00:00

commit 55da97e38cab844682abb71400a908b871d0054c upstream.

In clock driver initialize phase the spinlock is missed to assignment
to struct clkgate_separated, finally there have no locking to protect
exclusive accessing for clock registers.

This bug introduces the console has no output after enable coresight
driver on 96boards Hikey; this is because console using UART3, which
has shared the same register with coresight clock enabling bit. After
applied this patch it can assign lock properly to protect exclusive
accessing, and console can work well after enabled coresight modules.

Fixes: 0aa0c95f743a ("clk: hisilicon: add common clock support")
Signed-off-by: Leo Yan 
Signed-off-by: Stephen Boyd 
Signed-off-by: Ben Hutchings

clk: wm831x: fix usleep_range with bad range

2017-06-05T20:16:48+00:00

commit ed784c532a3d0959db488f40a96c5127f63d42dc upstream.

The delay here is not in atomic context and does not seem critical with
respect to precision, but usleep_range(min,max) with min==max results in
giving the timer subsystem no room to optimize uncritical delays. Fix
this by setting the range to 2000,3000 us.

Fixes: commit f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver")
Signed-off-by: Nicholas Mc Guire 
Acked-by: Charles Keepax 
Signed-off-by: Stephen Boyd 
Signed-off-by: Ben Hutchings

clk: renesas: mstp: Support 8-bit registers for r7s72100

2017-03-16T02:26:39+00:00

commit e2a33c34ddff22ee208d80abdd12b88a98d6cb60 upstream.

The RZ/A1 is different than the other Renesas SOCs because the MSTP
registers are 8-bit instead of 32-bit and if you try writing values as
32-bit nothing happens...meaning this driver never worked for r7s72100.

Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi")
Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Acked-by: Kuninori Morimoto 
Signed-off-by: Stephen Boyd 
[bwh: Backported to 3.16: adjust filename]
Signed-off-by: Ben Hutchings

clk: clk-wm831x: fix a logic error

2017-03-16T02:26:31+00:00

commit 20979202ee6e4c68dab7bcf408787225a656d18e upstream.

Fix bug https://bugzilla.kernel.org/show_bug.cgi?id=188561. Function
wm831x_clkout_is_prepared() returns "true" when it fails to read
CLOCK_CONTROL_1. "true" means the device is already prepared. So
return "true" on the read failure seems improper.

Signed-off-by: Pan Bian 
Acked-by: Charles Keepax 
Fixes: f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver")
Signed-off-by: Stephen Boyd 
Signed-off-by: Ben Hutchings