linux-stable.git/drivers/clk, branch v3.16.40

clk: divider: Fix clk_divider_round_rate() to use clk_readl()

2017-02-23T03:53:55+00:00

commit 2cf9a57811bddb6fa6b0f8d7376da164d5534813 upstream.

clk-divider uses clk_readl()/clk_writel() everywhere, except in
clk_divider_round_rate(), where plain readl() is used. Change this to
clk_readl(), as it makes a difference on powerpc.

Fixes: e6d5e7d90be92cee ("clk-divider: Fix READ_ONLY when divider > 1")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: James Hogan 
Signed-off-by: Stephen Boyd 
[bwh: Backported to 3.16: adjust context]
Signed-off-by: Ben Hutchings

clk: xgene: Add missing parenthesis when clearing divider value

2016-04-30T22:05:53+00:00

commit 0f4c7a138dfefb0ebdbaf56e3ba2acd2958a6605 upstream.

In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.

Signed-off-by: Loc Ho 
Acked-by: Toan Le 
Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: Stephen Boyd 
Signed-off-by: Ben Hutchings

clk: versatile: sp810: support reentrance

2016-04-30T22:05:51+00:00

commit ec7957a6aa0aaf981fb8356dc47a2cdd01cde03c upstream.

Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.

Rename the timclken<0> .. timclken to sp810__
so every clock on every instance gets a unique name.

This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:

------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
  clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[] (unwind_backtrace) from []
             (show_stack+0x10/0x14)
[] (show_stack) from []
             (dump_stack+0x84/0x9c)
[] (dump_stack) from []
             (warn_slowpath_common+0x74/0xb0)
[] (warn_slowpath_common) from []
             (warn_slowpath_null+0x1c/0x24)
[] (warn_slowpath_null) from []
             (clk_sp810_of_setup+0x110/0x154)
[] (clk_sp810_of_setup) from []
             (of_clk_init+0x12c/0x1c8)
[] (of_clk_init) from []
             (time_init+0x20/0x2c)
[] (time_init) from []
             (start_kernel+0x244/0x3c4)
[] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---

Cc: Michael Turquette 
Cc: Pawel Moll 
Fixes: 6e973d2c4385 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij 
Signed-off-by: Stephen Boyd 
Signed-off-by: Ben Hutchings

clk: st: avoid uninitialized variable use

2016-02-02T19:27:05+00:00

commit 2dd52d7f6f9d9d03a82a68040ac3d221dd79af94 upstream.

quadfs_pll_fs660c32_round_rate prints a few structure members
that are never initialized, and also doesn't print the only one
it cares about. We get a gcc warning about the ones that
are printed:

clk/st/clkgen-fsyn.c:560:93: warning: 'params.sdiv' may be used uninitialized in this function
clk/st/clkgen-fsyn.c:560:93: warning: 'params.mdiv' may be used uninitialized in this function
clk/st/clkgen-fsyn.c:560:93: warning: 'params.pe' may be used uninitialized in this function
clk/st/clkgen-fsyn.c:560:93: warning: 'params.nsdiv' may be used uninitialized in this function

This changes the code to no longer print uninitialized data, and
for good measure it also prints the ndiv member that is being
set.

Signed-off-by: Arnd Bergmann 
Fixes: 5f7aa9071e93 ("clk: st: Support for QUADFS inside ClockGenB/C/D/E/F")
Acked-by: Gabriel Fernandez 
Signed-off-by: Stephen Boyd 
[ luis: backported to 3.16: adjusted context ]
Signed-off-by: Luis Henriques

clk: xgene: Fix divider with non-zero shift value

2016-02-02T19:23:10+00:00

commit 1382ea631ddddb634850a3795527db0feeff5aaf upstream.

The X-Gene clock driver missed the divider shift operation when
set the divider value.

Signed-off-by: Loc Ho 
Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd 
Signed-off-by: Luis Henriques

clk: versatile-icst: fix memory leak

2015-12-13T17:49:38+00:00

commit 7bdccef34fc67d3fce6778a018601dd41e43c5ce upstream.

A static code checker found a memory leak in the Versatile
ICST code. Fix it.

Fixes: a183da637c52 "clk: versatile: respect parent rate in ICST clock"
Reported-by: Stephen Boyd 
Signed-off-by: Linus Walleij 
Signed-off-by: Stephen Boyd 
Signed-off-by: Luis Henriques

clk: ti: fix dual-registration of uart4_ick

2015-10-30T13:59:27+00:00

commit 19e79687de22f23bcfb5e79cce3daba20af228d1 upstream.

On the OMAP AM3517 platform the uart4_ick gets registered
twice, causing any power management to /dev/ttyO3 to fail
when trying to wake the device up.

This solves the following oops:

[] Unhandled fault: external abort on non-linefetch (0x1028) at 0xfa09e008
[] PC is at serial_omap_pm+0x48/0x15c
[] LR is at _raw_spin_unlock_irqrestore+0x30/0x5c

Fixes: aafd900cab87 ("CLK: TI: add omap3 clock init file")
Cc: mturquette@baylibre.com
Cc: sboyd@codeaurora.org
Cc: linux-clk@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-kernel@lists.codethink.co.uk
Signed-off-by: Ben Dooks 
Signed-off-by: Tero Kristo 
Signed-off-by: Luis Henriques

clk: versatile: off by one in clk_sp810_timerclken_of_get()

2015-09-30T12:20:38+00:00

commit 3294bee87091be5f179474f6c39d1d87769635e2 upstream.

The ">" should be ">=" or we end up reading beyond the end of the array.

Fixes: 6e973d2c4385 ('clk: vexpress: Add separate SP810 driver')
Signed-off-by: Dan Carpenter 
Acked-by: Pawel Moll 
Signed-off-by: Stephen Boyd 
Signed-off-by: Luis Henriques

clk: exynos4: Fix wrong clock for Exynos4x12 ADC

2015-09-28T09:21:33+00:00

commit e323d56eb06b266b77c2b430cb5f1977ba549e03 upstream.

The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
However TSADC is present only on Exynos4210 so on Trats2 board (with
Exynos4412 SoC) the exynos-adc driver could not be probed:
   ERROR: could not get clock /adc@126C0000:adc(0)
   exynos-adc 126c0000.adc: failed getting clock, err = -2
   exynos-adc: probe of 126c0000.adc failed with error -2

Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
Converter is located in different register and it is named in datasheet
as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
is the same as purpose of TSADC from Exynos4210.

The patch adds gate clock for Exynos4x12 using the proper register so
backward compatibility is preserved. This fixes the probe of exynos-adc
driver on Exynos4x12 boards and allows accessing sensors connected to it
on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).

Signed-off-by: Krzysztof Kozlowski 
Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
Reviewed-by: Javier Martinez Canillas 
Acked-by: Tomasz Figa 
Signed-off-by: Stephen Boyd 
Signed-off-by: Luis Henriques

clk: ti: dra7-atl-clock: Fix possible ERR_PTR dereference

2015-07-15T09:01:15+00:00

commit e0cdcda508f110b7ec190dc7c5eb2869ba73a535 upstream.

of_clk_get_from_provider() returns ERR_PTR on failure. The
dra7-atl-clock driver was not checking its return value and
immediately used it in __clk_get_hw().  __clk_get_hw()
dereferences supplied clock, if it is not NULL, so in that case
it would dereference an ERR_PTR.

Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Krzysztof Kozlowski 
Signed-off-by: Stephen Boyd 
Signed-off-by: Luis Henriques