linux-stable.git/drivers/clk, branch v3.16.4

clk: qcom: Fix PLL rate configurations

2014-10-05T20:41:12+00:00

commit 5b6b7490af110c2b0df807eddd00ae6290bcf50a upstream.

Sometimes we need to program PLLs with a fixed rate
configuration during driver probe. Doing this after we register
the PLLs with the clock framework causes the common clock
framework to assume the rate of the PLLs are 0. This causes all
sorts of problems for rate recalculations because the common
clock framework caches the rate once at registration time unless
a flag is set to always recalculate the rates.

Split the qcom_cc_probe() function into two pieces, map and
everything else, so that drivers which need to configure some
PLL rates or otherwise twiddle bits in the clock controller can
do so before registering clocks. This allows us to properly
detect the rates of PLLs that are programmed at boot.

Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code"
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: mdp_lut_clk is a child of mdp_src

2014-10-05T20:41:12+00:00

commit f87dfcabc6f173cc811d185d33327f50a8c88399 upstream.

The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the
child of the mdp_src clock. Fix it.

Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Fix MN frequency tables, parent map, and jpegd

2014-10-05T20:41:12+00:00

commit ff20783f7b9f35b29e768d8ecc7076c1ca1a60ca upstream.

Clocks that don't have a pre-divider don't list any pre-divider
in their frequency tables, but their tables are initialized using
aggregate initializers. Use tagged initializers so we properly
assign the m and n values for each frequency. Furthermore, the
mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second
element to pll2 instead of pll8, causing the clock driver to
recalculate the wrong rate for any clocks using this array along
with a rate that uses pll2. Plus the .num_parents field is 3
instead of 4 so you can't even switch the parent to pll3. Finally
I noticed that the jpegd clock improperly indicates that the
pre-divider width is only 2, when it's actually 4 bits wide.

Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)"
Tested-by: Rob Clark 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: ti: divider: Provide error check for incoming parameters in set_rate

2014-10-05T20:41:12+00:00

commit 2f1032517623b70920d99529e5c87c8c680ab8bf upstream.

Check for valid parameters in check rate. Else, we end up getting errors
like:
[    0.000000] Division by zero in kernel.
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc1 #1
[    0.000000] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[    0.000000] [] (show_stack) from [] (dump_stack+0x78/0x94)
[    0.000000] [] (dump_stack) from [] (Ldiv0+0x8/0x10)
[    0.000000] [] (Ldiv0) from [] (ti_clk_divider_set_rate+0x14/0x14c)
[    0.000000] [] (ti_clk_divider_set_rate) from [] (clk_change_rate+0x138/0x180)
[    0.000000] [] (clk_change_rate) from [] (clk_change_rate+0x108/0x180)

This occurs as part of the inital clock tree update of child clock nodes
where new_rate could be 0 for non functional clocks.

Fixes: b4761198bfaf296 ("CLK: ti: add support for ti divider-clock")
Signed-off-by: Nishanth Menon 
Signed-off-by: Tero Kristo 
Signed-off-by: Greg Kroah-Hartman

clk: prevent erronous parsing of children during rate change

2014-10-05T20:41:12+00:00

commit 067bb1741c27c8d3b74ac98c0b8fc12b31e67005 upstream.

In some cases, clocks can switch their parent with clk_set_rate, for
example clk_mux can do this in some cases. Current implementation of
clk_change_rate uses un-safe list iteration on the clock children, which
will cause wrong clocks to be parsed in case any of the clock children
change their parents during the change rate operation. Fixed by using
the safe list iterator instead.

The problem was detected due to some divide by zero errors generated
by clock init on dra7-evm board, see discussion under
http://article.gmane.org/gmane.linux.ports.arm.kernel/349180 for details.

Fixes: 71472c0c06cf ("clk: add support for clock reparent on set_rate")
Signed-off-by: Tero Kristo 
Reported-by: Nishanth Menon 
Signed-off-by: Mike Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: ti: dra7-atl: Provide error check for incoming parameters in set_rate

2014-10-05T20:41:11+00:00

commit 20411dad75ece9a613af715df4489e60990c4017 upstream.

Check for valid parameters in check rate. Else, we end up getting
errors.

This occurs as part of the inital clock tree update of child clock
nodes where new_rate could be 0 for non functional clocks.

Fixes: 9ac33b0ce81fa48 (" CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Nishanth Menon 
Signed-off-by: Tero Kristo 
Signed-off-by: Greg Kroah-Hartman

clk: ti: clk-7xx: Correct ABE DPLL configuration

2014-07-31T15:36:58+00:00

ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.

Signed-off-by: Peter Ujfalusi 
Acked-by: Tero Kristo 
Signed-off-by: Mike Turquette

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux

2014-07-13T19:21:04+00:00

Pull clock driver fixes from Mike Turquette:
 "This batch of fixes is for a handful of clock drivers from Allwinner,
  Samsung, ST & TI.  Most of them are of the "this hardware won't work
  without this fix" variety, including patches that fix platforms that
  did not boot under certain configurations.  Other fixes are the result
  of changes to the clock core introduced in 3.15 that had subtle
  impacts on the clock drivers.

  There are no fixes to the clock framework core in this pull request"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
  clk: spear3xx: Set proper clock parent of uart1/2
  clk: spear3xx: Use proper control register offset
  clk: qcom: HDMI source sel is 3 not 2
  clk: sunxi: fix devm_ioremap_resource error detection code
  clk: s2mps11: Fix double free corruption during driver unbind
  clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
  clk: exynos5420: Remove aclk66_peric from the clock tree description
  clk/exynos5250: fix bit number for tv sysmmu clock
  clk: s3c64xx: Hookup SPI clocks correctly
  clk: samsung: exynos4: Remove SRC_MASK_ISP gates
  clk: samsung: add more aliases for s3c24xx
  clk: samsung: fix several typos to fix boot on s3c2410
  clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock
  clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
  clk: ti: dra7: return error code in failure case
  clk: ti: apll: not allocating enough data

clk: spear3xx: Set proper clock parent of uart1/2

2014-07-13T14:12:11+00:00

The uarts only work when the parent is ras_ahb_clk. The stale 3.5
based ST tree does this in the board file.

Add it to the clk init function. Not pretty, but the mess there is
amazing anyway.

Signed-off-by: Thomas Gleixner 
Acked-by: Viresh Kumar 
Signed-off-by: Mike Turquette

clk: spear3xx: Use proper control register offset

2014-07-13T14:11:40+00:00

The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock framework).

Signed-off-by: Thomas Gleixner 
Cc: stable@vger.kernel.org
Acked-by: Viresh Kumar 
Signed-off-by: Mike Turquette