linux-stable.git/drivers/clk, branch v3.12.22

clk: vexpress: NULL dereference on error path

2014-06-09T13:53:25+00:00

commit 6b4ed8b00e93bd31f24a25f59ed8d1b808d0cc00 upstream.

If the allocation fails then we dereference the NULL in the error path.
Just return directly.

Fixes: ed27ff1db869 ('clk: Versatile Express clock generators ("osc") driver')
Signed-off-by: Dan Carpenter 
Signed-off-by: Pawel Moll 
Signed-off-by: Jiri Slaby

clk: tegra: Fix wrong value written to PLLE_AUX

2014-06-06T10:38:18+00:00

commit d2c834abe2b39a2d5a6c38ef44de87c97cbb34b4 upstream.

The value written to PLLE_AUX was incorrect due to a wrong variable
being used. Without this fix SATA does not work.

Signed-off-by: Tuomas Tynkkynen 
Tested-by: Mikko Perttunen 
Reviewed-by: Thierry Reding 
Tested-by: Thierry Reding 
Acked-by: Thierry Reding 
Signed-off-by: Mike Turquette 
[mturquette@linaro.org: improved changelog]
Signed-off-by: Jiri Slaby

clk: tegra: use pll_ref as the pll_e parent

2014-06-06T08:17:52+00:00

commit 8e9cc80aa348938078c3c1a7ab55efb3c40990e3 upstream.

Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.

Signed-off-by: Peter De Schrijver 
Signed-off-by: Jiri Slaby

clk: s2mps11: Fix possible NULL pointer dereference

2014-05-15T07:55:41+00:00

commit 238e14055da87d0d012257788e39fe0df3a82226 upstream.

If parent device does not have of_node set the s2mps11_clk_parse_dt()
returned NULL. This NULL was later passed to of_clk_add_provider() which
dereferenced it in pr_debug() call.

Signed-off-by: Krzysztof Kozlowski 
Signed-off-by: Mike Turquette 
Signed-off-by: Jiri Slaby

clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

2014-01-15T23:31:42+00:00

commit 97c3557c3e0413efb1f021f582d1459760e22727 upstream.

The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.

Signed-off-by: Andrew Bresticker 
Signed-off-by: Sachin Kamat 
Acked-by: Mike Turquette 
Signed-off-by: Tomasz Figa 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

2014-01-15T23:31:42+00:00

commit 2feed5aecf5f367b92bd6b6e92afe9e3de466907 upstream.

The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.

Signed-off-by: Abhilash Kesavan 
Acked-by: Mike Turquette 
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos5250: Add MDMA0 clocks

2014-01-15T23:31:42+00:00

commit 8fb9aeb7a71ef4f3e0613d459a2e1366a7a90469 upstream.

Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.

Signed-off-by: Abhilash Kesavan 
Acked-by: Mike Turquette 
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos5250: Fix ACP gate register offset

2014-01-15T23:31:41+00:00

commit 3bf34666a0cce5234ac677ed2fbe5cea82c71329 upstream.

The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.

Signed-off-by: Abhilash Kesavan 
Acked-by: Mike Turquette 
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos4: Correct SRC_MFC register

2014-01-15T23:31:41+00:00

commit 5fdd1b56be51b1ec4dbde5b213d649ac717442da upstream.

The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.

Signed-off-by: Seung-Woo Kim 
Acked-by: Mike Turquette 
[t.figa: Updated patch description]
Signed-off-by: Tomasz Figa 
Signed-off-by: Greg Kroah-Hartman

clk: clk-divider: fix divisor > 255 bug

2014-01-15T23:31:41+00:00

commit 778037e1ccb75609846deca9e419449c1dc137fa upstream.

Commit 6d9252bd9a4bb (clk: Add support for power of two type dividers)
merged in v3.6 added the _get_val function to convert a divisor value to
a register field value depending on the flags. However it used the type
u8 for the div field, causing divisors larger than 255 to be masked
and the resultant clock rate to be too high.

E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down
to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This
was masked to 238 (0xee) resulting in a frequency of 103.26KHz.

Signed-off-by: James Hogan 
Cc: Rajendra Nayak 
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mike Turquette 
Signed-off-by: Greg Kroah-Hartman