linux-stable.git/drivers/clk, branch linux-4.5.y

clk: bcm2835: correctly enable fractional clock support

2016-06-08T01:18:50+00:00

commit 959ca92a3235fc4b17c1e18483fc390b3d612254 upstream.

The current driver calculates the clock divider with
fractional support enabled.

But it does not enable fractional support in the
control register itself resulting in an integer only divider,
but in clk_set_rate responds back the fractionally divided
clock frequency.

This patch enables fractional support in the control register
whenever there is a fractional bit set in the requested clock divider.

Mash clock limits are are also handled for the PWM clock
applying the correct divider limits (2 and max_int) applicable to
basic fractional divider support (mash order of 1).

It also adds locking to protect the read/modify/write cycle of
the register modification.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: divider value has to be 1 or more

2016-06-08T01:18:50+00:00

commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e upstream.

Current clamping of a normal divider allows a value < 1 to be valid.

A divider of < 1 would actually only be possible if we had a PLL...

So this patch clamps the divider to 1.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: pll_off should only update CM_PLL_ANARST

2016-06-08T01:18:50+00:00

commit 6727f086cfe4ddcc651eb2bf4301abfcf619be06 upstream.

bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
register, which may lose the other bits that are currently set by the
clock dividers.

It also now locks during the read/modify/write cycle of both
registers.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: at91: fix check of clk_register() returned value

2016-06-08T01:18:50+00:00

commit cb0ceaf77d93964a0d00477c79f4499123f6159c upstream.

The clk_register() function returns a valid pointer to struct clk or
ERR_PTR() error code, this makes a check for returned NULL value
useless and may lead to oops on error path.

Signed-off-by: Vladimir Zapolskiy 
Acked-by: Alexandre Belloni 
Acked-by: Boris Brezillon 
Fixes: bcc5fd49a0fd ("clk: at91: add a driver for the h32mx clock")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: Fix PLL poweron

2016-06-08T01:18:50+00:00

commit e708b383f4b94feca2e0d5d06e1cfc13cdfea100 upstream.

In poweroff, we set the reset bit and the power down bit, but only
managed to unset the reset bit for poweron.  This meant that if HDMI
did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the
PLLH (that had been on at boot time) and never recover.

Signed-off-by: Eric Anholt 
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

ARM: dts: imx35: restore existing used clock enumeration

2016-06-08T01:18:48+00:00

commit 3397c2c45b1b6f54834dfeae30a73046f33ca943 upstream.

A new element got inserted into enum mx35_clks with commit 3713e3f5e927
("clk: imx35: define two clocks for rtc"). This insertion shifted most
nummerical clock assignments to a new nummerical value which in turn
rendered most hardcoded nummeric values in imx35.dtsi incorrect.

Restore the existing order by moving the newly introduced clock to the
end of the enum. Update the dts documentation accordingly.

Signed-off-by: Alexander Kurz 
Fixes: 3713e3f5e927 ("clk: imx35: define two clocks for rtc")
Signed-off-by: Shawn Guo 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: add locking to pll*_on/off methods

2016-06-01T19:17:02+00:00

commit ec36a5c6682fdd5328abf15c3c67281bed0241d7 upstream.

Add missing locking to:
* bcm2835_pll_divider_on
* bcm2835_pll_divider_off
to protect the read modify write cycle for the
register access protecting both cm_reg and a2w_reg
registers.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: msm8916: Fix crypto clock flags

2016-06-01T19:16:58+00:00

commit 2a0974aa1a0b40a92387ea03dbfeacfbc9ba182c upstream.

This patch adds the CLK_SET_RATE_PARENT flag for the crypto core and
ahb blocks.  Without this flag, clk_set_rate can fail for certain
frequency requests.

Signed-off-by: Andy Gross 
Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: fix check of error code returned by devm_ioremap_resource()

2016-05-11T09:21:29+00:00

commit 4d3ac6662452060721599a3392bc2f524af984cb upstream.

The change fixes potential oops while accessing iomem on invalid
address, if devm_ioremap_resource() fails due to some reason.

The devm_ioremap_resource() function returns ERR_PTR() and never
returns NULL, which makes useless a following check for NULL.

Signed-off-by: Vladimir Zapolskiy 
Fixes: 5e63dcc74b30 ("clk: bcm2835: Add a driver for the auxiliary peripheral clock gates")
Reviewed-by: Eric Anholt 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: xgene: Add missing parenthesis when clearing divider value

2016-05-11T09:21:29+00:00

commit 0f4c7a138dfefb0ebdbaf56e3ba2acd2958a6605 upstream.

In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.

Signed-off-by: Loc Ho 
Acked-by: Toan Le 
Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman