linux-stable.git/drivers/clk, branch linux-4.1.y

clk: mvebu: armada-38x: add support for missing clocks

2018-05-23T01:36:34+00:00

[ Upstream commit 6a4a4595804548e173f0763a0e7274a3521c59a9 ]

Clearfog boards can come with a CPU clocked at 1600MHz (commercial)
or 1333MHz (industrial).

They have also some dip-switches to select a different clock (666, 800,
1066, 1200).

The funny thing is that the recovery button is on the MPP34 fq selector.
So, when booting an industrial board with this button down, the frequency
666MHz is selected (and the kernel didn't boot).

This patch add all the missing clocks.

The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ).

Fixes: 0e85aeced4d6 ("clk: mvebu: add clock support for Armada 380/385")
Cc:  # 3.16.x: 9593f4f56cf5: clk: mvebu: armada-38x: add support for 1866MHz variants
Cc:  # 3.16.x

Signed-off-by: Richard Genoud 
Acked-by: Gregory CLEMENT 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: mvebu: armada-38x: add support for 1866MHz variants

2018-05-23T01:36:34+00:00

[ Upstream commit 9593f4f56cf5d1c443f66660a0c7f01de38f979d ]

The Linksys WRT3200ACM CPU is clocked at 1866MHz. Add 1866MHz to the
list of supported CPU frequencies. Also update multiplier and divisor
for the l2clk and ddrclk.

Noticed by the following warning:
[    0.000000] Selected CPU frequency (16) unsupported

Signed-off-by: Ralph Sennhauser 
Reviewed-by: Gregory CLEMENT 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: si5351: Rename internal plls to avoid name collisions

2018-05-23T01:33:52+00:00

[ Upstream commit cdba9a4fb0b53703959ac861e415816cb61aded4 ]

This drivers probe fails due to a clock name collision if a clock named
'plla' or 'pllb' is already registered when registering this drivers
internal plls.

Fix it by renaming internal plls to avoid name collisions.

Cc: Sebastian Hesselbarth 
Cc: Rabeeh Khoury 
Signed-off-by: Sergej Sawazki 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: tegra: Fix cclk_lp divisor register

2018-01-17T17:55:38+00:00

[ Upstream commit 54eff2264d3e9fd7e3987de1d7eba1d3581c631e ]

According to comments in code and common sense, cclk_lp uses its
own divisor, not cclk_g's.

Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30")
Signed-off-by: Michał Mirosław 
Acked-By: Peter De Schrijver 
Signed-off-by: Thierry Reding 
Signed-off-by: Sasha Levin

clk: ti: dra7-atl-clock: fix child-node lookups

2017-12-08T23:01:05+00:00

[ Upstream commit 33ec6dbc5a02677509d97fe36cd2105753f0f0ea ]

Fix child node-lookup during probe, which ended up searching the whole
device tree depth-first starting at parent rather than just matching on
its children.

Note that the original premature free of the parent node has already
been fixed separately, but that fix was apparently never backported to
stable.

Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Fixes: 660e15519399 ("clk: ti: dra7-atl-clock: Fix of_node reference counting")
Cc: stable      # 3.16: 660e15519399
Cc: Peter Ujfalusi 
Signed-off-by: Johan Hovold 
Acked-by: Peter Ujfalusi 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: ti: dra7-atl-clock: Fix of_node reference counting

2017-12-08T23:01:05+00:00

[ Upstream commit 660e1551939931657808d47838a3f443c0e83fd0 ]

of_find_node_by_name() will call of_node_put() on the node so we need to
get it first to avoid warnings.
The cfg_node needs to be put after we have finished processing the
properties.

Signed-off-by: Peter Ujfalusi 
Tested-by: Nishanth Menon 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: qcom: msm8916: Fix crypto clock flags

2016-07-11T03:07:26+00:00

[ Upstream commit 2a0974aa1a0b40a92387ea03dbfeacfbc9ba182c ]

This patch adds the CLK_SET_RATE_PARENT flag for the crypto core and
ahb blocks.  Without this flag, clk_set_rate can fail for certain
frequency requests.

Signed-off-by: Andy Gross 
Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: qcom: msm8960: Fix ce3_src register offset

2016-07-11T03:07:18+00:00

[ Upstream commit 0f75e1a370fd843c9e508fc1ccf0662833034827 ]

The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.

Tested-by: Srinivas Kandagatla 
Tested-by: Bjorn Andersson 
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: versatile: sp810: support reentrance

2016-07-11T03:07:17+00:00

[ Upstream commit ec7957a6aa0aaf981fb8356dc47a2cdd01cde03c ]

Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.

Rename the timclken<0> .. timclken to sp810__
so every clock on every instance gets a unique name.

This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:

------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
  clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[] (unwind_backtrace) from []
             (show_stack+0x10/0x14)
[] (show_stack) from []
             (dump_stack+0x84/0x9c)
[] (dump_stack) from []
             (warn_slowpath_common+0x74/0xb0)
[] (warn_slowpath_common) from []
             (warn_slowpath_null+0x1c/0x24)
[] (warn_slowpath_null) from []
             (clk_sp810_of_setup+0x110/0x154)
[] (clk_sp810_of_setup) from []
             (of_clk_init+0x12c/0x1c8)
[] (of_clk_init) from []
             (time_init+0x20/0x2c)
[] (time_init) from []
             (start_kernel+0x244/0x3c4)
[] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---

Cc: Michael Turquette 
Cc: Pawel Moll 
Fixes: 6e973d2c4385 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: qcom: msm8960: fix ce3_core clk enable register

2016-07-11T03:07:17+00:00

[ Upstream commit 732d6913691848db9fabaa6a25b4d6fad10ddccf ]

This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla 
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin