linux-stable.git/drivers/clk, branch linux-3.19.y

clk: at91: usb: fix determine_rate prototype

2015-05-11T12:34:02+00:00

Commit c67881fc890916206e723329e774391c6ed354ce is a backport of
0b67c43ce36a9964f1d5e3f973ee19eefd3f9f8f upstream commit, fixing a
bug on clk rate change propagation.
But in 4.0 ->determine_rate() prototype has changed, thus introducing
a prototype mismatch when applying it on 3.19.

Signed-off-by: Boris Brezillon 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: fix RCG M/N counter configuration

2015-05-06T20:01:59+00:00

commit 0b21503dbbfa669dbd847b33578d4041513cddb2 upstream.

Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.

Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.

Signed-off-by: Archit Taneja 
Fixes: bcd61c0f535a (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Fix i2c frequency table

2015-05-06T20:01:59+00:00

commit 0bf0ff82c34da02ee5795101b328225a2d519594 upstream.

PXO is 25MHz, not 27MHz. Fix the table.

Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global
clock controller (GCC)"

Signed-off-by: Stephen Boyd 
Reviewed-by: Andy Gross 
Tested-by: Andy Gross 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: tegra: Register the proper number of resets

2015-05-06T20:01:59+00:00

commit 5e43e259171e1eee8bc074d9c44be434e685087b upstream.

The number of resets controls is 32 times the number of peripheral
register banks rather than 32 times the number of clocks. This reduces
(drastically) the number of reset controls registered from 10080 (315
clocks * 32) to 224 (6 peripheral register banks * 32).

This also fixes a potential crash because trying to use any of the
excess reset controls (224-10079) would have caused accesses beyond
the array bounds of the peripheral register banks definition array.

Cc: Peter De Schrijver 
Cc: Prashant Gaikwad 
Fixes: 6d5b988e7dc5 ("clk: tegra: implement a reset driver")
Signed-off-by: Thierry Reding 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos4: Disable ARMCLK down feature on Exynos4210 SoC

2015-05-06T20:01:59+00:00

commit 3a9e9cb65be84d6c64fbe9c69a73c15d59f29454 upstream.

Commit 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK
down feature") enabled ARMCLK down feature on all Exynos4
SoCs.  Unfortunately on Exynos4210 SoC ARMCLK down feature
causes a lockup when ondemand cpufreq governor is used.
Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs.

This patch was tested on:
- Exynos4210 SoC based Trats board
- Exynos4210 SoC based Origen board
- Exynos4412 SoC based Trats2 board
- Exynos4412 SoC based Odroid-U3 board

Cc: Daniel Drake 
Cc: Tomasz Figa 
Cc: Kukjin Kim 
Fixes: 42773b28e71d ("clk: samsung: exynos4: Enable ARMCLK down feature")
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Bartlomiej Zolnierkiewicz 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: at91: usb: propagate rate modification to the parent clk

2015-05-06T20:01:52+00:00

commit 4591243102faa8de92da320edea47219901461e9 upstream.

The at91sam9n12 and at91sam9x5 usb clocks do not propagate rate
modification requests to their parents.
This causes a bug when the PLLB is left uninitialized by the bootloader
(PLL multiplier set to 0, or in other words, PLL rate = 0 Hz).

Implement the determinate_rate method and propagate the change rate
request to the parent clk.

Signed-off-by: Boris Brezillon 
Reported-by: Bo Shen 
Tested-by: Bo Shen 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: divider: fix calculation of maximal parent rate for a given divider

2015-04-19T08:10:26+00:00

commit da321133b53caf7889ed3ca1dabe4cc368db2604 upstream.

The rate provided at the output of a clk-divider is calculated as:

	DIV_ROUND_UP(parent_rate, div)

since commit b11d282dbea2 (clk: divider: fix rate calculation for
fractional rates). So to yield a rate not bigger than r parent_rate
must be <= r * div.

The effect of choosing a parent rate that is too big as was done before
this patch results in wrongly ruling out good dividers.

Note that this is not a complete fix as __clk_round_rate might return a
value >= its 2nd parameter. Also for dividers with
CLK_DIVIDER_ROUND_CLOSEST set the calculation is not accurate. But this
fixes the test case by Sascha Hauer that uses a chain of three dividers
under a fixed clock.

Fixes: b11d282dbea2 (clk: divider: fix rate calculation for fractional rates)
Suggested-by: Sascha Hauer 
Signed-off-by: Uwe Kleine-König 
Acked-by: Sascha Hauer 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: divider: fix selection of divider when rounding to closest

2015-04-19T08:10:26+00:00

commit 26bac95aa88c2b1747808c0b885abe7814c0165d upstream.

It's an invalid approach to assume that among two divider values
the one nearer the exact divider is the better one.

Assume a parent rate of 1000 Hz, a divider with CLK_DIVIDER_POWER_OF_TWO
and a target rate of 89 Hz. The exact divider is ~ 11.236 so 8 and 16
are the candidates to choose from yielding rates 125 Hz and 62.5 Hz
respectivly. While 8 is nearer to 11.236 than 16 is, the latter is still
the better divider as 62.5 is nearer to 89 than 125 is.

Fixes: 774b514390b1 (clk: divider: Add round to closest divider)
Signed-off-by: Uwe Kleine-König 
Acked-by: Sascha Hauer 
Acked-by: Maxime Coquelin 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk-gate: fix bit # check in clk_register_gate()

2015-03-18T13:11:12+00:00

commit 2e9dcdae4068460c45a308dd891be5248260251c upstream.

In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit #
should be no higher than 15, however the corresponding check is obviously off-
by-one.

Fixes: 045779942c04 ("clk: gate: add CLK_GATE_HIWORD_MASK")
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

sunxi: clk: Set sun6i-pll1 n_start = 1

2015-03-18T13:11:07+00:00

commit 76820fcf7aa5a418b69cb7bed31b62d1feb1d6ad upstream.

For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as
it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set
for sun6i pll6, but was missing for pll1, this commit fixes this.

Cc: Chen-Yu Tsai 
Signed-off-by: Hans de Goede 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman