linux-stable.git/drivers/clk, branch linux-3.10.y

clk: clk-wm831x: fix a logic error

2017-06-07T22:46:53+00:00

commit 20979202ee6e4c68dab7bcf408787225a656d18e upstream.

Fix bug https://bugzilla.kernel.org/show_bug.cgi?id=188561. Function
wm831x_clkout_is_prepared() returns "true" when it fails to read
CLOCK_CONTROL_1. "true" means the device is already prepared. So
return "true" on the read failure seems improper.

Signed-off-by: Pan Bian 
Acked-by: Charles Keepax 
Fixes: f05259a6ffa4 ("clk: wm831x: Add initial WM831x clock driver")
Signed-off-by: Stephen Boyd 
Signed-off-by: Willy Tarreau

clk: versatile: sp810: support reentrance

2016-06-07T08:42:52+00:00

commit ec7957a6aa0aaf981fb8356dc47a2cdd01cde03c upstream.

Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.

Rename the timclken<0> .. timclken to sp810__
so every clock on every instance gets a unique name.

This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:

------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
  clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[] (unwind_backtrace) from []
             (show_stack+0x10/0x14)
[] (show_stack) from []
             (dump_stack+0x84/0x9c)
[] (dump_stack) from []
             (warn_slowpath_common+0x74/0xb0)
[] (warn_slowpath_common) from []
             (warn_slowpath_null+0x1c/0x24)
[] (warn_slowpath_null) from []
             (clk_sp810_of_setup+0x110/0x154)
[] (clk_sp810_of_setup) from []
             (of_clk_init+0x12c/0x1c8)
[] (of_clk_init) from []
             (time_init+0x20/0x2c)
[] (time_init) from []
             (start_kernel+0x244/0x3c4)
[] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---

Cc: Michael Turquette 
Cc: Pawel Moll 
Fixes: 6e973d2c4385 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Willy Tarreau

clk: versatile: off by one in clk_sp810_timerclken_of_get()

2015-09-21T17:00:07+00:00

commit 3294bee87091be5f179474f6c39d1d87769635e2 upstream.

The ">" should be ">=" or we end up reading beyond the end of the array.

Fixes: 6e973d2c4385 ('clk: vexpress: Add separate SP810 driver')
Signed-off-by: Dan Carpenter 
Acked-by: Pawel Moll 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: sunxi: Support factor clocks with N factor starting not from 0

2015-03-18T12:22:34+00:00

commit 9a5e6c7eb5ccbb5f0d3a1dffce135f0a727f40e1 upstream.

The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.

This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Signed-off-by: Maxime Ripard 
Signed-off-by: Greg Kroah-Hartman

clk: spear3xx: Use proper control register offset

2014-07-17T22:58:02+00:00

commit 15ebb05248d025534773c9ef64915bd888f04e4b upstream.

The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock framework).

Signed-off-by: Thomas Gleixner 
Acked-by: Viresh Kumar 
Signed-off-by: Mike Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: vexpress: NULL dereference on error path

2014-06-07T20:25:35+00:00

commit 6b4ed8b00e93bd31f24a25f59ed8d1b808d0cc00 upstream.

If the allocation fails then we dereference the NULL in the error path.
Just return directly.

Fixes: ed27ff1db869 ('clk: Versatile Express clock generators ("osc") driver')
Signed-off-by: Dan Carpenter 
Signed-off-by: Pawel Moll 
Signed-off-by: Greg Kroah-Hartman

clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

2014-01-15T23:28:52+00:00

commit 97c3557c3e0413efb1f021f582d1459760e22727 upstream.

The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.

Signed-off-by: Andrew Bresticker 
Signed-off-by: Sachin Kamat 
Acked-by: Mike Turquette 
Signed-off-by: Tomasz Figa 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock

2014-01-15T23:28:52+00:00

commit 2feed5aecf5f367b92bd6b6e92afe9e3de466907 upstream.

The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.

Signed-off-by: Abhilash Kesavan 
Acked-by: Mike Turquette 
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa 
Signed-off-by: Greg Kroah-Hartman

clk: samsung: exynos4: Correct SRC_MFC register

2014-01-15T23:28:52+00:00

commit 5fdd1b56be51b1ec4dbde5b213d649ac717442da upstream.

The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.

Signed-off-by: Seung-Woo Kim 
Acked-by: Mike Turquette 
[t.figa: Updated patch description]
Signed-off-by: Tomasz Figa 
Signed-off-by: Greg Kroah-Hartman

clk: clk-divider: fix divisor > 255 bug

2014-01-15T23:28:52+00:00

commit 778037e1ccb75609846deca9e419449c1dc137fa upstream.

Commit 6d9252bd9a4bb (clk: Add support for power of two type dividers)
merged in v3.6 added the _get_val function to convert a divisor value to
a register field value depending on the flags. However it used the type
u8 for the div field, causing divisors larger than 255 to be masked
and the resultant clock rate to be too high.

E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down
to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This
was masked to 238 (0xee) resulting in a frequency of 103.26KHz.

Signed-off-by: James Hogan 
Cc: Rajendra Nayak 
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mike Turquette 
Signed-off-by: Greg Kroah-Hartman