linux-stable.git/drivers/clk/tegra, branch v4.2 Linux kernel stable tree clk: tegra: Fix hda2codec_2x clock name for Tegra30 2015-05-13T13:17:14+00:00 Marcel Ziswiler marcel.ziswiler@toradex.com 2015-04-10T21:35:57+00:00 36b7be6d3ea8f434f1e0723f3fb0e85c3e00ebc2 The HDA to codec clock is named hda2codec_2x, so use the proper name in the clock table. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
The HDA to codec clock is named hda2codec_2x, so use the proper name in
the clock table.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: EMC clock driver depends on EMC driver 2015-05-13T13:17:13+00:00 Thierry Reding treding@nvidia.com 2015-04-01T07:10:58+00:00 31b52ba42d71e9ed8ee544e64c340ec6c571272f The EMC clock driver uses symbols exported by the EMC driver, so it needs the corresponding dependency to avoid build breakage. Signed-off-by: Thierry Reding <treding@nvidia.com> 
The EMC clock driver uses symbols exported by the EMC driver, so it
needs the corresponding dependency to avoid build breakage.

Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Have EMC clock implement determine_rate() 2015-05-13T13:17:13+00:00 Tomeu Vizoso tomeu.vizoso@collabora.com 2015-03-17T09:36:13+00:00 890d6a54ead9dafdfdeebe65cbb10056e14c835a As opposed to round_rate(), determine_rate() can take rate constraints into account when choosing the best rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
As opposed to round_rate(), determine_rate() can take rate constraints
into account when choosing the best rate.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Set the EMC clock as the parent of the MC clock 2015-05-13T13:17:12+00:00 Tomeu Vizoso tomeu.vizoso@collabora.com 2015-03-12T14:48:07+00:00 ac67477f8f4163a6e7678f252030051f4eef2d5f On Tegra124, as we now have a proper driver for the EMC. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
On Tegra124, as we now have a proper driver for the EMC.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Add EMC clock driver 2015-05-13T13:17:11+00:00 Mikko Perttunen mperttunen@nvidia.com 2015-03-12T14:48:05+00:00 2db04f16b589c6c96bd07df3f1ef8558bfdb6810 The driver is currently only tested on Tegra124 Jetson TK1, but should work with other Tegra124 boards, provided that correct EMC tables are provided through the device tree. Older chip models have differing timing change sequences, so they are not currently supported. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> [treding@nvidia.com: use more consistent function names] Signed-off-by: Thierry Reding <treding@nvidia.com> 
The driver is currently only tested on Tegra124 Jetson TK1, but should
work with other Tegra124 boards, provided that correct EMC tables are
provided through the device tree. Older chip models have differing
timing change sequences, so they are not currently supported.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
[treding@nvidia.com: use more consistent function names]
Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Remove old Tegra124 EMC clock 2015-05-13T13:17:10+00:00 Mikko Perttunen mperttunen@nvidia.com 2015-03-12T14:47:53+00:00 374ffadaf3abd4bf77073bd8f1acf0ada7dc797e This clock has never been able to do anything. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
This clock has never been able to do anything.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Use the proper parent for plld_dsi 2015-04-10T14:04:22+00:00 Thierry Reding treding@nvidia.com 2015-03-26T16:53:01+00:00 c1d676cec572544616273d5853cb7cc38fbaa62b The current parent, plld_out0, does not exist. The proper name is pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to be more consistent with other clock names. Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux") Signed-off-by: Thierry Reding <treding@nvidia.com> 
The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.

Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Use generic tegra_osc_clk_init() on Tegra114 2015-04-10T14:04:21+00:00 Thierry Reding treding@nvidia.com 2015-03-26T16:50:06+00:00 a84724a1c3cccd03b4ca1c8aea135095d0a6204e There is no reason why Tegra114 cannot use the same generic code to set up the oscillator, clk_m and pll_ref clocks. The only effective change that this causes is that the CLK_SET_PARENT_RATE flag is dropped, but since these clocks are all fixed it is not needed anyway. Signed-off-by: Thierry Reding <treding@nvidia.com> 
There is no reason why Tegra114 cannot use the same generic code to set
up the oscillator, clk_m and pll_ref clocks. The only effective change
that this causes is that the CLK_SET_PARENT_RATE flag is dropped, but
since these clocks are all fixed it is not needed anyway.

Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Model oscillator as clock 2015-04-10T14:04:20+00:00 Thierry Reding treding@nvidia.com 2015-03-26T16:43:56+00:00 63cc5a4da1fafedee24d8f5af67c1dd9d08f95c7 Currently the Tegra clock driver simplifies the clock tree somewhat by taking advantage of the fact that clk_m runs at the same frequency as the oscillator. While that's true on all currently supported SoCs, it does not apply to Tegra210 anymore. On Tegra210 clk_m is typically divided down from the oscillator frequency. To support that setup, add a separate clock for the oscillator that both clk_m and pll_ref derive from. Modify the tegra_osc_clk_init() function to take an additional divider parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210 will read the divider from a register in the clock & reset controller. Signed-off-by: Thierry Reding <treding@nvidia.com> 
Currently the Tegra clock driver simplifies the clock tree somewhat by
taking advantage of the fact that clk_m runs at the same frequency as
the oscillator. While that's true on all currently supported SoCs, it
does not apply to Tegra210 anymore. On Tegra210 clk_m is typically
divided down from the oscillator frequency. To support that setup, add
a separate clock for the oscillator that both clk_m and pll_ref derive
from.

Modify the tegra_osc_clk_init() function to take an additional divider
parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210
will read the divider from a register in the clock & reset controller.

Signed-off-by: Thierry Reding <treding@nvidia.com>
clk: tegra: Add peripheral registers for bank Y 2015-04-10T14:04:20+00:00 Thierry Reding treding@nvidia.com 2015-03-23T09:52:45+00:00 699b477a0d3a5bc68034a1520a4337ea0a20f63b Tegra210 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Tegra210 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>