linux-stable.git/drivers/clk/tegra, branch linux-4.3.y

clk: tegra: dfll: Properly protect OPP list

2015-09-16T22:16:03+00:00

The OPP list needs to be protected against concurrent accesses. Using
simple RCU read locks does the trick and gets rid of the following
lockdep warning:

	===============================
	[ INFO: suspicious RCU usage. ]
	4.2.0-next-20150908 #1 Not tainted
	-------------------------------
	drivers/base/power/opp.c:460 Missing rcu_read_lock() or dev_opp_list_lock protection!

	other info that might help us debug this:

	rcu_scheduler_active = 1, debug_locks = 0
	4 locks held by kworker/u8:0/6:
	 #0:  ("%s""deferwq"){++++.+}, at: [] process_one_work+0x118/0x4bc
	 #1:  (deferred_probe_work){+.+.+.}, at: [] process_one_work+0x118/0x4bc
	 #2:  (&dev->mutex){......}, at: [] __device_attach+0x20/0x118
	 #3:  (prepare_lock){+.+...}, at: [] clk_prepare_lock+0x10/0xf8

	stack backtrace:
	CPU: 2 PID: 6 Comm: kworker/u8:0 Not tainted 4.2.0-next-20150908 #1
	Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
	Workqueue: deferwq deferred_probe_work_func
	[] (unwind_backtrace) from [] (show_stack+0x10/0x14)
	[] (show_stack) from [] (dump_stack+0x94/0xd4)
	[] (dump_stack) from [] (dev_pm_opp_find_freq_ceil+0x108/0x114)
	[] (dev_pm_opp_find_freq_ceil) from [] (dfll_calculate_rate_request+0xb8/0x170)
	[] (dfll_calculate_rate_request) from [] (dfll_clk_round_rate+0x1c/0x2c)
	[] (dfll_clk_round_rate) from [] (clk_calc_new_rates+0x1b8/0x228)
	[] (clk_calc_new_rates) from [] (clk_core_set_rate_nolock+0x44/0xac)
	[] (clk_core_set_rate_nolock) from [] (clk_set_rate+0x24/0x34)
	[] (clk_set_rate) from [] (tegra124_cpufreq_probe+0x120/0x230)
	[] (tegra124_cpufreq_probe) from [] (platform_drv_probe+0x44/0xac)
	[] (platform_drv_probe) from [] (driver_probe_device+0x218/0x304)
	[] (driver_probe_device) from [] (bus_for_each_drv+0x60/0x94)
	[] (bus_for_each_drv) from [] (__device_attach+0xb4/0x118)
	ata1: SATA link down (SStatus 0 SControl 300)
	[] (__device_attach) from [] (bus_probe_device+0x88/0x90)
	[] (bus_probe_device) from [] (deferred_probe_work_func+0x58/0x8c)
	[] (deferred_probe_work_func) from [] (process_one_work+0x188/0x4bc)
	[] (process_one_work) from [] (worker_thread+0x4c/0x4f4)
	[] (worker_thread) from [] (kthread+0xe4/0xf8)
	[] (kthread) from [] (ret_from_fork+0x14/0x24)

Signed-off-by: Thierry Reding 
Fixes: c4fe70ada40f ("clk: tegra: Add closed loop support for the DFLL")
[vince.h@nvidia.com: Unlock rcu on error path]
Signed-off-by: Vince Hsu 
[sboyd@codeaurora.org: Dropped second hunk that nested the rcu
read lock unnecessarily]
Signed-off-by: Stephen Boyd

clk: tegra: Fix some static checker problems

2015-08-25T23:03:42+00:00

The latest Tegra clk pull had some problems. Fix them.

drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static?
drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting
drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td->i2c_lut[0]' is never less than zero.

Signed-off-by: Stephen Boyd

Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

2015-08-25T22:55:28+00:00

clk: tegra: Changes for v4.3-rc1

This contains the DFLL driver needed to implement CPU frequency scaling
on Tegra.

clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

2015-08-24T23:49:12+00:00

Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.

@@
struct clk_hw *E;
@@

-__clk_get_name(E->clk)
+clk_hw_get_name(E)

Acked-by: Heiko Stuebner 
Cc: Sylwester Nawrocki 
Cc: Tomasz Figa 
Cc: Peter De Schrijver 
Cc: Prashant Gaikwad 
Cc: Stephen Warren 
Acked-by: Thierry Reding 
Cc: Thierry Reding 
Cc: Alexandre Courbot 
Cc: Tero Kristo 
Cc: Ulf Hansson 
Acked-by: Sebastian Hesselbarth 
Acked-by: Andrew Bresticker 
Cc: Ezequiel Garcia 
Cc: Ralf Baechle 
Cc: Kevin Cernekee 
Acked-by: Geert Uytterhoeven 
Cc: Ulrich Hecht 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Stephen Boyd

clk: tegra: Convert to clk_hw based provider APIs

2015-08-24T23:48:57+00:00

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Tomeu Vizoso 
Cc: Thierry Reding 
Signed-off-by: Stephen Boyd

Merge branch 'cleanup-clk-h-includes' into clk-next

2015-07-28T18:59:09+00:00

* cleanup-clk-h-includes: (62 commits)
  clk: Remove clk.h from clk-provider.h
  clk: h8300: Remove clk.h and clkdev.h includes
  clk: at91: Include clk.h and slab.h
  clk: ti: Switch clk-provider.h include to clk.h
  clk: pistachio: Include clk.h
  clk: ingenic: Include clk.h
  clk: si570: Include clk.h
  clk: moxart: Include clk.h
  clk: cdce925: Include clk.h
  clk: Include clk.h in clk.c
  clk: zynq: Include clk.h
  clk: ti: Include clk.h
  clk: sunxi: Include clk.h and remove unused clkdev.h includes
  clk: st: Include clk.h
  clk: qcom: Include clk.h
  clk: highbank: Include clk.h
  clk: bcm: Include clk.h
  clk: versatile: Remove clk.h and clkdev.h includes
  clk: ux500: Remove clk.h and clkdev.h includes
  clk: tegra: Properly include clk.h
  ...

clk: change clk_ops' ->determine_rate() prototype

2015-07-28T01:12:01+00:00

Clock rates are stored in an unsigned long field, but ->determine_rate()
(which returns a rounded rate from a requested one) returns a long
value (errors are reported using negative error codes), which can lead
to long overflow if the clock rate exceed 2Ghz.

Change ->determine_rate() prototype to return 0 or an error code, and pass
a pointer to a clk_rate_request structure containing the expected target
rate and the rate constraints imposed by clk users.

The clk_rate_request structure might be extended in the future to contain
other kind of constraints like the rounding policy, the maximum clock
inaccuracy or other things that are not yet supported by the CCF
(power consumption constraints ?).

Signed-off-by: Boris Brezillon 
CC: Jonathan Corbet 
CC: Tony Lindgren 
CC: Ralf Baechle 
CC: "Emilio López" 
CC: Maxime Ripard 
Acked-by: Tero Kristo 
CC: Peter De Schrijver 
CC: Prashant Gaikwad 
CC: Stephen Warren 
CC: Thierry Reding 
CC: Alexandre Courbot 
CC: linux-doc@vger.kernel.org
CC: linux-kernel@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-omap@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: linux-tegra@vger.kernel.org
[sboyd@codeaurora.org: Fix parent dereference problem in
__clk_determine_rate()]
Signed-off-by: Stephen Boyd 
Tested-by: Romain Perier 
Signed-off-by: Heiko Stuebner 
[sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate
clocks without parents or a rate determining op]
Signed-off-by: Stephen Boyd

clk: tegra: Properly include clk.h

2015-07-20T18:11:17+00:00

Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h include that was missing in a file
using clkdev APIs.

Cc: Peter De Schrijver 
Cc: Thierry Reding 
Signed-off-by: Stephen Boyd

clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

2015-07-16T08:40:20+00:00

The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.

Signed-off-by: Tuomas Tynkkynen 
Signed-off-by: Mikko Perttunen 
Acked-by: Michael Turquette 
Signed-off-by: Thierry Reding

clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend

2015-07-16T08:40:19+00:00

Save and restore this register since the LP1 restore assembly routines
fiddle with it. Otherwise the CPU would keep running on PLLX after
resume from suspend even when DFLL was the original clocksource.

Signed-off-by: Tuomas Tynkkynen 
Signed-off-by: Mikko Perttunen 
Acked-by: Peter De Schrijver 
Acked-by: Michael Turquette 
Signed-off-by: Thierry Reding