linux-stable.git/drivers/clk/starfive, branch v6.7

Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next

2023-08-30T21:37:45+00:00

 - Remove OXNAS clk driver

* clk-bindings:
  dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml
  dt-bindings: clock: xlnx,versal-clk: drop select:false
  dt-bindings: clock: versal: Add versal-net compatible string
  dt-bindings: clock: ast2600: Add I3C and MAC reset definitions
  dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding

* clk-starfive:
  reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support
  clk: starfive: Simplify .determine_rate()
  clk: starfive: Add StarFive JH7110 Video-Output clock driver
  clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
  clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
  clk: starfive: jh7110-sys: Add PLL clocks source from DTS
  clk: starfive: Add StarFive JH7110 PLL clock driver
  dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
  dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
  dt-bindings: soc: starfive: Add StarFive syscon module
  dt-bindings: clock: Add StarFive JH7110 PLL clock generator

* clk-rm:
  dt-bindings: clk: oxnas: remove obsolete bindings
  clk: oxnas: remove obsolete clock driver

* clk-renesas:
  clk: renesas: rcar-gen3: Add ADG clocks
  clk: renesas: r8a77965: Add 3DGE and ZG support
  clk: renesas: r8a7796: Add 3DGE and ZG support
  clk: renesas: r8a7795: Add 3DGE and ZG support
  clk: renesas: emev2: Remove obsolete clkdev registration
  clk: renesas: r9a07g043: Add MTU3a clock and reset entry
  clk: renesas: rzg2l: Simplify .determine_rate()
  clk: renesas: r9a09g011: Add CSI related clocks
  clk: renesas: r8a774b1: Add 3DGE and ZG support
  clk: renesas: r8a774e1: Add 3DGE and ZG support
  clk: renesas: r8a774a1: Add 3DGE and ZG support
  clk: renesas: rcar-gen3: Add support for ZG clock

* clk-cleanup:
  clk: mvebu: Convert to devm_platform_ioremap_resource()
  clk: nuvoton: Convert to devm_platform_ioremap_resource()
  clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
  clk: ti: Use devm_platform_get_and_ioremap_resource()
  clk: mediatek: Convert to devm_platform_ioremap_resource()
  clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
  clk: gemini: Convert to devm_platform_ioremap_resource()
  clk: fsl-sai: Convert to devm_platform_ioremap_resource()
  clk: bm1880: Convert to devm_platform_ioremap_resource()
  clk: axm5516: Convert to devm_platform_ioremap_resource()
  clk: actions: Convert to devm_platform_ioremap_resource()
  clk: cdce925: Remove redundant of_match_ptr()
  drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init()
  clk: Explicitly include correct DT includes

clk: Explicitly include correct DT includes

2023-07-19T20:13:16+00:00

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Acked-by: Dinh Nguyen 
Acked-by: Krzysztof Kozlowski  # samsung
Acked-by: Heiko Stuebner  #rockchip
Acked-by: Chanwoo Choi 
Acked-by: Geert Uytterhoeven 
Reviewed-by: AngeloGioacchino Del Regno 
Reviewed-by: Luca Ceresoli  # versaclock5
Signed-off-by: Rob Herring 
Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org
Acked-by: Abel Vesa  #imx
Signed-off-by: Stephen Boyd

clk: starfive: Simplify .determine_rate()

2023-07-19T19:50:42+00:00

jh71x0_clk_mux_determine_rate() is the same as __clk_mux_determine_rate(),
so use the latter to save some LoC.

Signed-off-by: Christophe JAILLET 
Link: https://lore.kernel.org/r/085541814ebe2543cb7e8a31004c0da3e7d5b6eb.1688760111.git.christophe.jaillet@wanadoo.fr
Reviewed-by: Emil Renner Berthing 
Signed-off-by: Stephen Boyd

clk: starfive: Add StarFive JH7110 Video-Output clock driver

2023-07-19T17:08:05+00:00

Add driver for the StarFive JH7110 Video-Output clock controller.
And these clock controllers should power on and enable the clocks from
SYSCRG first before registering.

Acked-by: Palmer Dabbelt 
Reviewed-by: Emil Renner Berthing 
Reviewed-by: Hal Feng 
Signed-off-by: Xingyu Wu 
Signed-off-by: Conor Dooley

clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver

2023-07-19T17:08:05+00:00

Add driver for the StarFive JH7110 Image-Signal-Process clock controller.
And these clock controllers should power on and enable the clocks from
SYSCRG before registering.

Acked-by: Palmer Dabbelt 
Reviewed-by: Emil Renner Berthing 
Reviewed-by: Hal Feng 
Signed-off-by: Xingyu Wu 
Signed-off-by: Conor Dooley

clk: starfive: Add StarFive JH7110 System-Top-Group clock driver

2023-07-19T17:08:05+00:00

Add driver for the StarFive JH7110 System-Top-Group clock controller.

Acked-by: Palmer Dabbelt 
Reviewed-by: Hal Feng 
Co-developed-by: Xingyu Wu 
Signed-off-by: Xingyu Wu 
Signed-off-by: Emil Renner Berthing 
Signed-off-by: Conor Dooley

clk: starfive: jh7110-sys: Add PLL clocks source from DTS

2023-07-19T17:08:00+00:00

Modify PLL clocks source to be got from DTS or
the fixed factor clocks.

Signed-off-by: Xingyu Wu 
Reviewed-by: Emil Renner Berthing 
Signed-off-by: Conor Dooley

clk: starfive: Add StarFive JH7110 PLL clock driver

2023-07-19T17:08:00+00:00

Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.

Co-developed-by: Emil Renner Berthing 
Signed-off-by: Emil Renner Berthing 
Signed-off-by: Xingyu Wu 
Signed-off-by: Conor Dooley

clk: starfive: Fix RESET_STARFIVE_JH7110 can't be selected in a specified case

2023-05-03T01:34:49+00:00

When (ARCH_STARFIVE [=n] && COMPILE_TEST [=y] && RESET_CONTROLLER [=n]),
RESET_STARFIVE_JH7110 can't be selected by CLK_STARFIVE_JH7110_SYS
and CLK_STARFIVE_JH7110_AON.

Add a condition `if RESET_CONTROLLER` to fix it. Also, delete redundant
selected options of CLK_STARFIVE_JH7110_AON because these options are
already selected by the dependency.

Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock driver")
Fixes: b2ab3c94f41f ("clk: starfive: Add StarFive JH7110 always-on clock driver")
Signed-off-by: Hal Feng 
Link: https://lore.kernel.org/r/20230418123756.62495-2-hal.feng@starfivetech.com
Reviewed-by: Conor Dooley 
Signed-off-by: Stephen Boyd

clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers

2023-04-18T01:14:10+00:00

The dev_set_drvdata() is no longer needed after we used a wrapper
struct to get the data in auxiliary driver.

Cc: Xingyu Wu 
Fixes: d1aae0663023 ("clk: starfive: Avoid casting iomem pointers")
Signed-off-by: Hal Feng 
Link: https://lore.kernel.org/r/20230417074115.30786-3-hal.feng@starfivetech.com
Signed-off-by: Stephen Boyd