linux-stable.git/drivers/clk/rockchip, branch v6.2

Merge branches 'clk-spear', 'clk-fract', 'clk-rockchip' and 'clk-imx' into clk-next

2022-12-12T19:13:08+00:00

 - Debugfs support for fractional divider clk

* clk-spear:
  clk: spear: Fix SSP clock definition on SPEAr600
  clk: spear: Fix CLCD clock definition on SPEAr600

* clk-fract:
  clk: fractional-divider: Regroup inclusions
  clk: fractional-divider: Show numerator and denominator in debugfs
  clk: fractional-divider: Split out clk_fd_get_div() helper

* clk-rockchip:
  clk: rockchip: Fix memory leak in rockchip_clk_register_pll()
  clk: rockchip: add clock controller for the RK3588
  clk: rockchip: add lookup table support
  clk: rockchip: simplify rockchip_clk_add_lookup
  clk: rockchip: allow additional mux options for cpu-clock frequency changes
  clk: rockchip: add pll type for RK3588
  clk: rockchip: add register offset of the cores select parent
  dt-bindings: clock: add rk3588 cru bindings
  dt-bindings: reset: add rk3588 reset definitions
  dt-bindings: clock: add rk3588 clock definitions
  clk: rockchip: use proper crypto0 name on rk3399

* clk-imx:
  clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()
  clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
  clk: imx8mn: fix imx8mn_sai2_sels clocks list
  clk: imx: rename video_pll1 to video_pll
  clk: imx: replace osc_hdmi with dummy
  clk: imx8mn: rename vpu_pll to m7_alt_pll
  clk: imx: imxrt1050: add IMXRT1050_CLK_LCDIF_PIX clock gate
  clk: imx: imxrt1050: fix IMXRT1050_CLK_LCDIF_APB offsets
  clk: imx8mp: Add audio shared gate
  dt-bindings: clock: imx8mp: Add ids for the audio shared gate
  clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x
  clk: imx93: keep sys ctr clock always on
  clk: imx: keep hsio bus clock always on
  clk: imx93: drop tpm1/3, lpit1/2 clk
  dt-bindings: clock: imx93: drop TPM1/3 LPIT1/2 entry
  clk: imx93: correct enet clock
  clk: imx93: unmap anatop base in error handling path
  clk: imx: imx8mp: add shared clk gate for usb suspend clk
  dt-bindings: clocks: imx8mp: Add ID for usb suspend clock
  clk: imx93: correct the flexspi1 clock setting

clk: rockchip: Fix memory leak in rockchip_clk_register_pll()

2022-11-23T13:51:30+00:00

If clk_register() fails, @pll->rate_table may have allocated memory by
kmemdup(), so it needs to be freed, otherwise will cause memory leak
issue, this patch fixes it.

Fixes: 90c590254051 ("clk: rockchip: add clock type for pll clocks and pll used on rk3066")
Signed-off-by: Xiu Jianfeng 
Link: https://lore.kernel.org/r/20221123091201.199819-1-xiujianfeng@huawei.com
Signed-off-by: Heiko Stuebner

clk: Remove a useless include

2022-11-23T01:52:07+00:00

 is not needed for these drivers. Remove the
corresponding #include.

Signed-off-by: Christophe JAILLET 
Link: https://lore.kernel.org/r/12dd5cb49efa7714f8e0389e4c7b3bc829e8a90e.1668289299.git.christophe.jaillet@wanadoo.fr
Acked-by: Heiko Stuebner 
Acked-by: Jerome Brunet 
Reviewed-by: Luca Ceresoli 
Signed-off-by: Stephen Boyd

clk: rockchip: add clock controller for the RK3588

2022-11-15T10:37:41+00:00

Add full clock controller support RK3588.

[rebase, integrate fixes from Wyon and Finley, add missing frequencies
 to PLL lookup table, update commit message, add GATE_LINK clocks which
 downstream handles in its own driver with one DT node per clock]

Signed-off-by: Wyon Bi 
Signed-off-by: Finley Xiao 
Signed-off-by: Elaine Zhang 
Signed-off-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com
[dropped module stuff after talking to Sebastian]
Signed-off-by: Heiko Stuebner

clk: rockchip: add lookup table support

2022-11-14T14:35:07+00:00

Add support for mapping reset IDs to register offsets
to support gapless continous platform reset IDs.

Signed-off-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20221018151407.63395-9-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner

clk: rockchip: simplify rockchip_clk_add_lookup

2022-11-14T14:35:07+00:00

rockchip_clk_add_lookup is only called from within the file,
so it can be made static. The additional checks are removed
with the following reasoning:

1. The data structure is initialized by rockchip_clk_init(),
   which is called by all rockchip platforms before the clocks
   are registered. Not doing so would result in an incomplete
   clock tree at the moment, which is a fatal error. In other
   parts of the kernel these kind of checks are usually
   omitted, so this was done here. The alternative is adding
   a pr_err to inform the kernel programmer adding a new platform
   about his incorrect code. Apart from that we are also not
   checking if the clock id is within the array boundings.

2. While not used so far by any rockchip platform, 0 is a valid
   clock identifier. To align rockchip closer to other ARM
   platforms we will start using it with rk3588.

Signed-off-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20221018151407.63395-8-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner

clk: rockchip: allow additional mux options for cpu-clock frequency changes

2022-11-14T14:34:18+00:00

In order to improve the main frequency of CPU, the clock path of CPU is
simplified as follows:
                         |--\
                         |   \            |--\
 --apll--|\              |    \           |   \
         | |--apll_core--|     \          |    \
 --24M---|/              |mux1 |--[gate]--|mux2|---clk_core
                         |     /          |    /
 --gpll--|\              |    /    |------|   /
         | |--gpll_core--|   /     |      |--/
 --24M---|/              |--/      |
                                   |
 -------apll_directly--------------|

When the CPU requests high frequency, we want to use MUX2 select the
"apll_directly".
At low frequencies use MUX1 to select “apll_core" and then MUX2 to
select "apll_core_gate".

However, in this way, the CPU frequency conversion needs to be
in the following order:
1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
sets normal_mode
3. MUX1 select "apll_core", MUX2 select "apll_directly"

So add pre_mux and post_mux options to cover this special requirements.

Signed-off-by: Elaine Zhang 
[rebase]
Signed-off-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner

clk: rockchip: add pll type for RK3588

2022-11-14T14:33:46+00:00

Add RK3588 PLL support fully relying on lookup tables like
the other upstream supported rockchip platforms.

Signed-off-by: Elaine Zhang 
[rebase and modify code to avoid PLL parameter calculation]
Signed-off-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20221018151407.63395-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner

clk: rockchip: add register offset of the cores select parent

2022-11-14T14:33:45+00:00

The cores select parent register is special on RK3588.

Signed-off-by: Elaine Zhang 
Signed-off-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner

clk: rockchip: Add clock controller support for RV1126 SoC

2022-09-23T09:15:30+00:00

Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
and CRU_PMU blocks.

This patch is trying to add minimal Clock-Architecture Diagram's
inferred from [1] authored by Finley Xiao.

[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c

Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette 
Cc: Stephen Boyd 
Signed-off-by: Finley Xiao 
Signed-off-by: Jagan Teki 
Link: https://lore.kernel.org/r/20220915163947.1922183-5-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner