linux-stable.git/drivers/clk/rockchip, branch linux-4.3.y

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2015-09-20T03:17:40+00:00

Pull clk fixes from Stephen Boyd:
 "A few driver fixes for tegra, rockchip, and st SoCs and a two-liner in
  the framework to avoid oops when get_parent ops return out of range
  values on tegra platforms"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
  clk: check for invalid parent index of orphans in __clk_init()
  clk: tegra: dfll: Properly protect OPP list
  clk: rockchip: add critical clock for rk3368

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2015-09-14T23:58:35+00:00

Pull clk fixes from Stephen Boyd:
 "A couple build fixes for drivers introduced in the merge window and a
  handful of patches to add more critical clocks on rockchip SoCs that
  are affected by newly introduced gpio clock handling"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188
  clk: rockchip: add pclk_cpu to the list of rk3188 critical clocks
  clk: rockchip: handle critical clocks after registering all clocks
  clk: Hi6220: separately build stub clock driver
  clk: h8s2678: Fix compile error

clk: rockchip: add critical clock for rk3368

2015-09-14T19:49:39+00:00

Again a result of the gpio-clock-liberation the rk3368 needs the
pclk_pd_pmu marked as critical, to boot successfully.

Reported-by: Mark Rutland 
Signed-off-by: Heiko Stuebner 
Tested-by: Mark Rutland 
Signed-off-by: Stephen Boyd

clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188

2015-09-10T20:55:30+00:00

Now that the rockchip clock subsystem does clock gating with GPIO banks,
these are no longer enabled once during probe and no longer stay enabled
for eternity. When all these clocks are disabled, the parent clock pclk_peri
might be disabled too, as no other child claims it. So, we need to add pclk_peri
to the critical clocks.

Signed-off-by: Romain Perier 
Tested-by: Michael Niewoehner 
Signed-off-by: Stephen Boyd

clk: rockchip: add pclk_cpu to the list of rk3188 critical clocks

2015-09-10T20:55:28+00:00

pclk_cpu needs to keep running because it is needed for devices like
the act8865 regulator but with the recent gpio clock handling this is
not always the case anymore. So add it to the list of critical clocks.

Signed-off-by: Michael Niewoehner 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd

clk: rockchip: handle critical clocks after registering all clocks

2015-09-10T20:55:21+00:00

Currently the registration of critical clocks is done in the function
shared between rk3066 and rk3188 clock trees. That results in them
getting handled maybe before all of them are registered.

Therefore move the critical clock handling down to the end of the soc-
specific clock registration function, so that all clocks are registered
before they're maybe handled as critical clock.

Signed-off-by: Heiko Stuebner 
Tested-by: Michael Niewoehner 
Signed-off-by: Stephen Boyd

Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2015-09-04T17:22:09+00:00

Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.3 development
cycle.

Like with GPIO it's a lot of stuff. If my subsystems are any sign of
the overall tempo of the kernel v4.3 will be a gigantic diff.

[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
we'll see - Linus ]

Core changes:

- It is possible configure groups in debugfs.

- Consolidation of chained IRQ handler install/remove replacing all
call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a combined
call to irq_set_chained_handler_and_data(). This series was
created by Thomas Gleixner after the problem was observed by
Russell King.

- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which is
way cleaner.

- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs from
IRQ numbers. The goal is to get rid of the irq number from the
handlers in the IRQ flow which is nice.

Driver feature enhancements:

- Power management support for the SiRF SoC Atlas 7.

- Power down support for the Qualcomm driver.

- Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
in IRQ handlers to play nice with the realtime patch set.

- Rework and new modes handling for Qualcomm SPMI-MPP.

- Pinconf power source config for SH PFC.

New drivers and subdrivers:

- A new driver for Conexant Digicolor CX92755.

- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
ProXtream2 and PH1-LD6b SoC pin control support.

- Reverse-egineered the S/PDIF settings for the Allwinner sun4i
driver.

- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs

- A new Freescale i.mx6ul subdriver.

Cleanup:

- Remove platform data support in a number of SH PFC subdrivers"

* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
pinctrl: at91: fix null pointer dereference
pinctrl: mediatek: Implement wake handler and suspend resume
pinctrl: mediatek: Fix multiple registration issue.
pinctrl: sh-pfc: r8a7794: add USB pin groups
pinctrl: at91: Use generic irq_{request,release}_resources()
pinctrl: cherryview: Use raw_spinlock for locking
pinctrl: baytrail: Use raw_spinlock for locking
pinctrl: imx6ul: Remove .owner field
pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pinctrl: sun4i: add spdif to pin description.
pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
pinctrl: baytrail: Serialize all register access
pinctrl: baytrail: Drop FSF mailing address
pinctrl: rockchip: only enable gpio clock when it setting
pinctrl/mediatek: fix spelling mistake in dev_err error message
pinctrl: cherryview: Serialize all register access
pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
pinctrl: nomadik: reflect current input value
...

clk: rockchip: register pll mux before pll itself

2015-08-24T23:49:15+00:00

The structure is xin24m -> pll -> pll-mux (xin24m,pll,xin32k). The pll
does have an init callback to make sure the boot-selected frequency is
using the expected pll settings and resets the same frequency using
the values provided in the driver if necessary.

The setting itself also involves remuxing the pll-mux temporarily to
the xin24m source to let the new pll rate settle. Until now this worked
flawlessly, even when it had the flaw of accessing the mux settings
before the mux actually got registered.

With the recent clock-core conversions this flaw became apparent in
null pointer dereference in
[] (clk_hw_get_num_parents) from [] (clk_mux_get_parent+0x14/0xc8)
[] (clk_mux_get_parent) from [] (rockchip_rk3066_pll_set_rate+0xd8/0x320)

So to fix that, simply register the pll-mux before the pll, so that
it will be fully initialized when the pll clock executes its init-
callback and possibly touches the pll-mux clock.

Signed-off-by: Heiko Stuebner 
Signed-off-by: Michael Turquette

clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)

2015-08-24T23:49:12+00:00

Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.

@@
struct clk_hw *E;
@@

-__clk_get_name(E->clk)
+clk_hw_get_name(E)

Acked-by: Heiko Stuebner 
Cc: Sylwester Nawrocki 
Cc: Tomasz Figa 
Cc: Peter De Schrijver 
Cc: Prashant Gaikwad 
Cc: Stephen Warren 
Acked-by: Thierry Reding 
Cc: Thierry Reding 
Cc: Alexandre Courbot 
Cc: Tero Kristo 
Cc: Ulf Hansson 
Acked-by: Sebastian Hesselbarth 
Acked-by: Andrew Bresticker 
Cc: Ezequiel Garcia 
Cc: Ralf Baechle 
Cc: Kevin Cernekee 
Acked-by: Geert Uytterhoeven 
Cc: Ulrich Hecht 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Stephen Boyd

clk: rockchip: Convert to clk_hw based provider APIs

2015-08-24T23:48:53+00:00

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Reviewed-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd