linux-stable.git/drivers/clk/qcom, branch v6.4.3 Linux kernel stable tree clk: qcom: gcc-sc8280xp: Add EMAC GDSCs 2023-04-24T14:22:01+00:00 Andrew Halaney ahalaney@redhat.com 2023-04-13T19:15:39+00:00 32c2f2a46db1322caaf78d5ea747ed5c56d2e353 Add the EMAC GDSCs to allow the EMAC hardware to be enabled. Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413191541.1073027-2-ahalaney@redhat.com 
Add the EMAC GDSCs to allow the EMAC hardware to be enabled.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230413191541.1073027-2-ahalaney@redhat.com
clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk 2023-04-14T03:36:20+00:00 Konrad Dybcio konrad.dybcio@linaro.org 2023-04-12T14:53:06+00:00 68d1151f03067533827fc50b770954ef33149533 There's only one DSI PHY on this SoC. Remove the ghost entry for the clock produced by a secondary one. Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v1-2-bf2989a75ae4@linaro.org 
There's only one DSI PHY on this SoC. Remove the ghost entry for the
clock produced by a secondary one.

Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v1-2-bf2989a75ae4@linaro.org
clk: qcom: add the GPUCC driver for sa8775p 2023-04-14T03:36:09+00:00 Shazad Hussain quic_shazhuss@quicinc.com 2023-04-11T12:59:05+00:00 0afa16afc36d0e462c7f815b0131d2e9013849ac Add the clock driver for the Qualcomm Graphics Clock control module. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> [Bartosz: make ready for upstream] Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230411125910.401075-3-brgl@bgdev.pl 
Add the clock driver for the Qualcomm Graphics Clock control module.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
[Bartosz: make ready for upstream]
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230411125910.401075-3-brgl@bgdev.pl
clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling 2023-04-14T03:35:53+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2023-04-12T13:48:29+00:00 1a500e0bc97b6cb3c0d9859e81973b8dd07d1b7b On SM8350 platform the PCIe PIPE clocks require additional handling to function correctly. They are to be switched to the tcxo source before turning PCIe GDSCs off and should be switched to PHY PIPE source once they are working. Switch PCIe PHY clocks to use clk_regmap_phy_mux_ops, which provide support for this dance. Fixes: 44c20c9ed37f ("clk: qcom: gcc: Add clock driver for SM8350") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412134829.3686467-1-dmitry.baryshkov@linaro.org 
On SM8350 platform the PCIe PIPE clocks require additional handling to
function correctly. They are to be switched to the tcxo source before
turning PCIe GDSCs off and should be switched to PHY PIPE source once
they are working. Switch PCIe PHY clocks to use clk_regmap_phy_mux_ops,
which provide support for this dance.

Fixes: 44c20c9ed37f ("clk: qcom: gcc: Add clock driver for SM8350")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230412134829.3686467-1-dmitry.baryshkov@linaro.org
clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc 2023-04-14T03:17:12+00:00 Mohammad Rafi Shaik quic_mohs@quicinc.com 2023-04-07T09:22:55+00:00 aad09fc7c4a522892eb64a79627b17a3869936cb Add GDSCs in lpass_cc_sc7280_desc struct. When qcom,adsp-pil-mode is enabled, GDSCs required to solve dependencies in lpass_audiocc probe(). Fixes: 0cbcfbe50cbf ("clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon") Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407092255.119690-4-quic_mohs@quicinc.com 
Add GDSCs in lpass_cc_sc7280_desc struct.
When qcom,adsp-pil-mode is enabled, GDSCs required to solve
dependencies in lpass_audiocc probe().

Fixes: 0cbcfbe50cbf ("clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon")
Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230407092255.119690-4-quic_mohs@quicinc.com
clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration 2023-04-14T03:17:12+00:00 Srinivasa Rao Mandadapu quic_srivasam@quicinc.com 2023-04-07T09:22:54+00:00 4fc1c2d9a2b7a394f3b873aae5e03bffd8b5cd31 The qdsp6ss memory region is being shared by ADSP remoteproc device and lpasscc clock device, hence causing memory conflict. To avoid this, when qdsp6ss clocks are being enabled in remoteproc driver, skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled and also assign max_register value. Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280") Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407092255.119690-3-quic_mohs@quicinc.com 
The qdsp6ss memory region is being shared by ADSP remoteproc device and
lpasscc clock device, hence causing memory conflict.
To avoid this, when qdsp6ss clocks are being enabled in remoteproc driver,
skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled and
also assign max_register value.

Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230407092255.119690-3-quic_mohs@quicinc.com
clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` 2023-04-12T15:24:49+00:00 Lars-Peter Clausen lars@metafoo.de 2023-04-10T01:44:58+00:00 f1f67db9d64ffb85af04dbbf59e3f213fbf86add Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230410014502.27929-7-lars@metafoo.de 
Use the managed `devm_of_clk_add_hw_provider()` instead of
`of_clk_add_hw_provider()`.

This makes sure the provider gets automatically removed on unbind and
allows to completely eliminate the drivers `remove()` callback.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230410014502.27929-7-lars@metafoo.de
clk: qcom: Add Global Clock Controller driver for IPQ9574 2023-04-07T17:28:15+00:00 Devi Priya quic_devipriy@quicinc.com 2023-03-16T07:29:36+00:00 d75b82cff48883b5e75abfd3930afa7a148ab440 Add Global Clock Controller (GCC) driver for ipq9574 based devices Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316072940.29137-3-quic_devipriy@quicinc.com 
Add Global Clock Controller (GCC) driver for ipq9574 based devices

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316072940.29137-3-quic_devipriy@quicinc.com
clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value 2023-04-07T16:27:02+00:00 Konrad Dybcio konrad.dybcio@linaro.org 2023-03-29T14:01:35+00:00 93f21d925f787eb4a91e7ade77a544df30be0605 Configure the disable wait value on the CX GDSC to ensure we don't get any undefined behavior. This was omitted when first adding the driver. Fixes: 8397e24278b3 ("clk: qcom: Add GPU clock controller driver for SM6375") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230329140135.2178957-1-konrad.dybcio@linaro.org 
Configure the disable wait value on the CX GDSC to ensure we don't get
any undefined behavior. This was omitted when first adding the driver.

Fixes: 8397e24278b3 ("clk: qcom: Add GPU clock controller driver for SM6375")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230329140135.2178957-1-konrad.dybcio@linaro.org
clk: qcom: gcc-sm6115: Mark RCGs shared where applicable 2023-04-07T16:18:24+00:00 Konrad Dybcio konrad.dybcio@linaro.org 2023-04-04T22:47:19+00:00 996c32b745a15a637e8244a25f06b74acce98976 The vast majority of shared RCGs were not marked as such. Fix it. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230404224719.909746-1-konrad.dybcio@linaro.org 
The vast majority of shared RCGs were not marked as such. Fix it.

Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230404224719.909746-1-konrad.dybcio@linaro.org