linux-stable.git/drivers/clk/qcom, branch v6.0

clk: qcom: gcc-msm8994: use parent_hws for gpll0/4

2022-07-19T02:40:36+00:00

Use parent_hws for two remaining clocks in gcc-msm8994 that used
parent_names.

Signed-off-by: Dmitry Baryshkov 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220620080505.1573948-1-dmitry.baryshkov@linaro.org

clk: qcom: clk-rpm: convert to parent_data API

2022-07-19T00:13:27+00:00

Convert clk-rpm driver to parent_data API.
We keep the old pxo/cxo_board parent naming to keep compatibility with
old DT and we use the new pxo/cxo for new implementation where these
clock are defined in DTS.

Signed-off-by: Christian Marangi 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220706225321.26215-4-ansuelsmth@gmail.com

clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies

2022-07-18T23:55:31+00:00

The shipped qcom driver defines:
static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
        F(  57140000,      gpll0_out_main,  14,    0,    0),
        F(  80000000,      gpll0_out_main,  10,   0,    0),
        F( 100000000,      gpll0_out_main,   8,   0,    0),
        F_END
};
In the upstream code we omit 57.14 MHz and 100 MHz.

Signed-off-by: Bryan O'Donoghue 
Reviewed-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220712125922.3461675-7-bryan.odonoghue@linaro.org

clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies

2022-07-18T23:55:31+00:00

Again the msm8936/msm8939 supports a wider range of operating frequencies
to the antecedent msm8916 from which the msm8939.c driver is derived.

static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
        F(  50000000,      gpll0_out_aux,  16,    0,    0),
        F(  80000000,      gpll0_out_aux,  10,    0,    0),
        F( 100000000,      gpll0_out_aux,   8,    0,    0),
        F( 145500000,      gpll0_out_aux,  5.5,   0,    0),
        F( 153600000,      gpll1_out_main,      4,      0,      0),
        F( 160000000,      gpll0_out_aux,   5,    0,    0),
        F( 177780000,      gpll0_out_aux, 4.5,    0,    0),
        F( 200000000,      gpll0_out_aux,   4,    0,    0),
        F( 266670000,      gpll0_out_aux,   3,    0,    0),
        F( 307200000,      gpll1_out_main,      2,      0,      0),
        F( 366670000,      gpll3_out_aux,   3,        0,    0),
        F_END
};

We are missing 145.5 MHz and 153.6 MHz.

Signed-off-by: Bryan O'Donoghue 
Reviewed-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220712125922.3461675-6-bryan.odonoghue@linaro.org

clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies

2022-07-18T23:55:31+00:00

Reviewing the qcom msm8936.c clock frequency tables we see

static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
        F( 160000000,      gpll0_out_main,   5,   0,    0),
        F( 200000000,      gpll0_out_main,   4,   0,    0),
        F( 228570000,      gpll0_out_main, 3.5,   0,    0),
        F( 266670000,      gpll0_out_main,   3,   0,    0),
        F( 320000000,      gpll0_out_main, 2.5,   0,    0),
        F( 465000000,      gpll2_out_main,   2,   0,    0),
        F_END
};
which is a super-set of the msm8916 original definitions.
Add in the missing frequency definitions now.

Signed-off-by: Bryan O'Donoghue 
Reviewed-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220712125922.3461675-5-bryan.odonoghue@linaro.org

clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions

2022-07-18T23:55:31+00:00

The Venus clock frequencies are a copy/paste error from msm8916. Looking
at the original clock-gcc-8936.c ftbl_gcc_venus0_vcodec0_clk defines we
have:

- 133 MHz
- 200 MHz
- 266 MHz

These values are born out by the relevant qualcomm documentation for the
msm8936/msm8939 Venus core performance levels.

Signed-off-by: Bryan O'Donoghue 
Reviewed-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220712125922.3461675-4-bryan.odonoghue@linaro.org

clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock

2022-07-18T23:55:31+00:00

Standard CCI bus clock clocks are 19.2 MHz and 37.5 MHz. We already define
the 19.2 MHz but are missing the 37.5 MHz.

See qcom kernel drivers/clk/qcom/clock-gcc-8936.c::ftbl_gcc_camss_cci_clk[]

Signed-off-by: Bryan O'Donoghue 
Reviewed-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220712125922.3461675-3-bryan.odonoghue@linaro.org

clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk

2022-07-18T23:55:31+00:00

Adding a new item to this frequency table I see the existing indentation is
incorrect.

Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue 
Reviewed-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220712125922.3461675-2-bryan.odonoghue@linaro.org

clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled

2022-07-18T21:35:48+00:00

When a GDSC is found to be enabled at boot the pm_runtime state will
be unbalanced as the GDSC is later turned off. Fix this by increasing
the usage counter on the power-domain, in line with how we handled the
regulator state.

Fixes: 1b771839de05 ("clk: qcom: gdsc: enable optional power domain support")
Signed-off-by: Bjorn Andersson 
Acked-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20220713212818.130277-1-bjorn.andersson@linaro.org

clk: qcom: Drop mmcx gdsc supply for dispcc and videocc

2022-07-18T21:35:03+00:00

Both dispcc and videocc use mmcx power domain now.
Lets drop the supply mmcx from every gdsc.

Cc: Dmitry Baryshkov 
Fixes: 266e5cf39a0f ("arm64: dts: qcom: sm8250: remove mmcx regulator")
Signed-off-by: Abel Vesa 
Reviewed-by: Dmitry Baryshkov 
Reviewed-by: Bjorn Andersson 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220713143200.3686765-1-abel.vesa@linaro.org