linux-stable.git/drivers/clk/qcom, branch v4.0.2

clk: qcom: Fix ipq806x LCC frequency tables

2015-05-06T20:03:59+00:00

commit b3261d768bcdd4b368179ed85becf38c95461848 upstream.

These frequency tables list the wrong rates. Either they don't
have the correct frequency at all, or they're specified in kHz
instead of Hz. Fix it.

Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
Tested-by: Kenneth Westfield 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: fix RCG M/N counter configuration

2015-05-06T20:03:58+00:00

commit 0b21503dbbfa669dbd847b33578d4041513cddb2 upstream.

Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.

Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.

Signed-off-by: Archit Taneja 
Fixes: bcd61c0f535a (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Properly change rates for ahbix clock

2015-05-06T20:03:58+00:00

commit 9d3745d44a7faa7d24db7facb1949a1378162f3e upstream.

The ahbix clock can never be turned off in practice. To change the
rates we need to switch the mux off the M/N counter to an always on
source (XO), reprogram the M/N counter to get the rate we want and
finally switch back to the M/N counter. Add a new ops structure
for this type of clock so that we can set the rate properly.

Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver"
Tested-by: Kenneth Westfield 
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: Fix i2c frequency table

2015-05-06T20:03:58+00:00

commit 0bf0ff82c34da02ee5795101b328225a2d519594 upstream.

PXO is 25MHz, not 27MHz. Fix the table.

Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global
clock controller (GCC)"

Signed-off-by: Stephen Boyd 
Reviewed-by: Andy Gross 
Tested-by: Andy Gross 
Signed-off-by: Michael Turquette 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: fix platform_no_drv_owner.cocci warnings

2015-02-25T20:14:35+00:00

drivers/clk/qcom/lcc-msm8960.c:577:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

Signed-off-by: Fengguang Wu 
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: qcom: fix platform_no_drv_owner.cocci warnings

2015-02-25T20:14:35+00:00

drivers/clk/qcom/lcc-ipq806x.c:465:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

CC: Rajendra Nayak 
Signed-off-by: Fengguang Wu 
Reviewed-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: qcom: Add PLL4 vote clock

2015-02-25T20:08:39+00:00

This clock is needed for most audio clock frequencies. Add it.

Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: qcom: lcc-msm8960: Fix PLL rate detection

2015-02-25T20:08:39+00:00

regmap_read() returns 0 on success, not the value of the register
that is read. Fix it so we properly detect the frequency plan.

Fixes: b82875ee07e5 "clk: qcom: Add MSM8960/APQ8064 LPASS clock
controller (LCC) driver"
Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: qcom: Fix slimbus n and m val offsets

2015-02-25T20:08:38+00:00

These shifts were copy/pasted from the pcm which is a different
size RCG. Use the correct offsets so that slimbus rates are
correct.

Fixes: b82875ee07e5 "clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver"
Signed-off-by: Stephen Boyd 
Signed-off-by: Michael Turquette

clk: Add rate constraints to clocks

2015-02-02T22:23:42+00:00

Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.

Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.

Signed-off-by: Tomeu Vizoso 
Signed-off-by: Stephen Boyd 
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: Michael Turquette 
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
                        migrated clk-private.h changes to clk.c]