linux-stable.git/drivers/clk/qcom, branch linux-6.3.y

clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk

2023-05-11T14:17:33+00:00

[ Upstream commit 68d1151f03067533827fc50b770954ef33149533 ]

There's only one DSI PHY on this SoC. Remove the ghost entry for the
clock produced by a secondary one.

Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v1-2-bf2989a75ae4@linaro.org
Signed-off-by: Sasha Levin

clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling

2023-05-11T14:17:32+00:00

[ Upstream commit 1a500e0bc97b6cb3c0d9859e81973b8dd07d1b7b ]

On SM8350 platform the PCIe PIPE clocks require additional handling to
function correctly. They are to be switched to the tcxo source before
turning PCIe GDSCs off and should be switched to PHY PIPE source once
they are working. Switch PCIe PHY clocks to use clk_regmap_phy_mux_ops,
which provide support for this dance.

Fixes: 44c20c9ed37f ("clk: qcom: gcc: Add clock driver for SM8350")
Signed-off-by: Dmitry Baryshkov 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20230412134829.3686467-1-dmitry.baryshkov@linaro.org
Signed-off-by: Sasha Levin

clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc

2023-05-11T14:17:32+00:00

[ Upstream commit aad09fc7c4a522892eb64a79627b17a3869936cb ]

Add GDSCs in lpass_cc_sc7280_desc struct.
When qcom,adsp-pil-mode is enabled, GDSCs required to solve
dependencies in lpass_audiocc probe().

Fixes: 0cbcfbe50cbf ("clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon")
Signed-off-by: Mohammad Rafi Shaik 
Reviewed-by: Stephen Boyd 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20230407092255.119690-4-quic_mohs@quicinc.com
Signed-off-by: Sasha Levin

clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration

2023-05-11T14:17:32+00:00

[ Upstream commit 4fc1c2d9a2b7a394f3b873aae5e03bffd8b5cd31 ]

The qdsp6ss memory region is being shared by ADSP remoteproc device and
lpasscc clock device, hence causing memory conflict.
To avoid this, when qdsp6ss clocks are being enabled in remoteproc driver,
skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled and
also assign max_register value.

Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280")
Signed-off-by: Srinivasa Rao Mandadapu 
Signed-off-by: Mohammad Rafi Shaik 
Reviewed-by: Stephen Boyd 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20230407092255.119690-3-quic_mohs@quicinc.com
Signed-off-by: Sasha Levin

clk: qcom: gcc-sm6115: Mark RCGs shared where applicable

2023-05-11T14:17:31+00:00

[ Upstream commit 996c32b745a15a637e8244a25f06b74acce98976 ]

The vast majority of shared RCGs were not marked as such. Fix it.

Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20230404224719.909746-1-konrad.dybcio@linaro.org
Signed-off-by: Sasha Levin

clk: qcom: gcc-qcm2290: Fix up gcc_sdcc2_apps_clk_src

2023-05-11T14:17:30+00:00

[ Upstream commit 1bf088a9f0e50acd175ba8deef0db11c099fa26e ]

Add the PARENT_ENABLE flag to prevent  the clock from getting stuck
at boot and use floor_ops to avoid SDHCI overclocking.

Fixes: 496d1a13d405 ("clk: qcom: Add Global Clock Controller driver for QCM2290")
Signed-off-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20230315173048.3497655-1-konrad.dybcio@linaro.org
Signed-off-by: Sasha Levin

clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREP

2023-02-23T01:38:56+00:00

Otherwise some configurations fail.

Fixes: 027726365906 ("clk: qcom: add the driver for the MSM8996 APCS clocks")
Link: https://lore.kernel.org/r/20230223013847.1218900-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd

clk: qcom: Revert sync_state based clk_disable_unused

2023-02-22T14:34:08+00:00

Revert the postponement of clk_disable_unused() for clock providers that
implement sync_state, and the change to drivers implementing this, until
agreement on the implementation has been reached.

This reverts:
29e31415e14e ("clk: qcom: Remove need for clk_ignore_unused on sc8280xp")
99c0f7d35c4b ("clk: qcom: sdm845: Use generic clk_sync_state_disable_unused callback")
26b36df75166 ("clk: Add generic sync_state callback for disabling unused clocks")

Requested-by: Stephen Boyd 
Signed-off-by: Bjorn Andersson

clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC

2023-02-09T01:48:55+00:00

The gdsc_init() function will rewrite the CLK_DIS_WAIT field while
registering the GDSC (writing the value 0x2 by default). This will
override the setting done in the driver's probe function.

Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe
function.

Fixes: 453361cdd757 ("clk: qcom: Add graphics clock controller driver for SDM845")
Reviewed-by: Stephen Boyd 
Signed-off-by: Dmitry Baryshkov 
Reviewed-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20230201172305.993146-2-dmitry.baryshkov@linaro.org

clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC

2023-02-09T01:48:55+00:00

The gdsc_init() function will rewrite the CLK_DIS_WAIT field while
registering the GDSC (writing the value 0x2 by default). This will
override the setting done in the driver's probe function.

Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe
function.

Fixes: 745ff069a49c ("clk: qcom: Add graphics clock controller driver for SC7180")
Reviewed-by: Stephen Boyd 
Signed-off-by: Dmitry Baryshkov 
Reviewed-by: Konrad Dybcio 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20230201172305.993146-1-dmitry.baryshkov@linaro.org