linux-stable.git/drivers/clk/qcom, branch linux-4.5.y

clk: qcom: msm8916: Fix crypto clock flags

2016-06-01T19:16:58+00:00

commit 2a0974aa1a0b40a92387ea03dbfeacfbc9ba182c upstream.

This patch adds the CLK_SET_RATE_PARENT flag for the crypto core and
ahb blocks.  Without this flag, clk_set_rate can fail for certain
frequency requests.

Signed-off-by: Andy Gross 
Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: msm8960: Fix ce3_src register offset

2016-05-11T09:21:29+00:00

commit 0f75e1a370fd843c9e508fc1ccf0662833034827 upstream.

The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.

Tested-by: Srinivas Kandagatla 
Tested-by: Bjorn Andersson 
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: qcom: msm8960: fix ce3_core clk enable register

2016-05-11T09:21:28+00:00

commit 732d6913691848db9fabaa6a25b4d6fad10ddccf upstream.

This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla 
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

Revert "clk: qcom: Specify LE device endianness"

2016-02-12T22:24:24+00:00

This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87.

The commit that caused us to specify LE device endianness here,
29bb45f25ff3 (regmap-mmio: Use native endianness for read/write,
2015-10-29), has been reverted in mainline so now when we specify
LE it actively breaks big endian kernels because the byte
swapping in regmap-mmio is incorrect. Let's revert this change
because it will 1) fix the big endian kernels and 2) be redundant
to specify LE because that will become the default soon.

Cc: Kevin Hilman 
Tested-by: Kevin Hilman 
Cc: Mark Brown 
Signed-off-by: Stephen Boyd

Merge branch 'clk-msm8996' into clk-next

2015-12-01T08:00:48+00:00

* clk-msm8996:
  clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver
  clk: qcom: Add gfx3d ping-pong PLL frequency switching
  clk: qcom: Add MSM8996 Global Clock Control (GCC) driver
  clk: qcom: Add Alpha PLL support
  clk: divider: Cap table divider values to 'width' member

clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver

2015-12-01T02:24:30+00:00

Add a driver for the multimedia clock controller found on MSM8996
based devices. This should allow most multimedia device drivers
to probe and control their clocks.

Signed-off-by: Stephen Boyd

clk: qcom: Add gfx3d ping-pong PLL frequency switching

2015-12-01T02:24:29+00:00

The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2,
MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624
MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To
make switching frequencies faster, we ping-pong between MMPLL2
and MMPLL8 when we're switching between frequencies that aren't
the maximum. Implement custom rcg clk ops for this type of
frequency switching.

Signed-off-by: Stephen Boyd

clk: qcom: Add MSM8996 Global Clock Control (GCC) driver

2015-12-01T02:24:27+00:00

Add support for the global clock controller found on MSM8996
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.

Signed-off-by: Stephen Boyd

clk: qcom: Add Alpha PLL support

2015-12-01T02:24:25+00:00

Add support for configuring rates of, enabling, and disabling
Alpha PLLs. This is sufficient for the types of PLLs found in
the global and multimedia clock controllers.

Signed-off-by: Stephen Boyd

clk: qcom: msm8916: Move xo and sleep clocks into DT

2015-11-21T00:40:47+00:00

Move the xo and sleep clocks to device-tree, instead of hard-coding
them in the driver. This allows us to insert the RPM clocks (if they
are enabled) in between the on-board oscillators and the actual clock.

Signed-off-by: Georgi Djakov 
Signed-off-by: Stephen Boyd