linux-stable.git/drivers/clk/nxp, branch linux-4.6.y

clk: add lpc18xx creg clk driver

2016-03-04T20:52:10+00:00

The CREG block on lpc18xx contains configuration register
for two low power clocks. Support enabling of these two
clocks with a clk driver that access CREG trough the
syscon regmap interface.

These clocks are needed to support peripherals like the
internal RTC on lpc18xx.

Signed-off-by: Joachim Eastwood 
Signed-off-by: Stephen Boyd

clk: lpc32xx: fix compilation warning

2016-03-03T19:41:43+00:00

Remove the following false positives compilation warning:
- drivers/clk/nxp/clk-lpc32xx.c: In function 'lpc32xx_clk_register':
  warning: 'hw' may be used uninitialized in this function [-Wmaybe-uninitialized]
- drivers/clk/nxp/clk-lpc32xx.c: In function 'clk_hclk_pll_round_rate':
  warning: 'p' may be used uninitialized in this function [-Wmaybe-uninitialized]
  warning: 'n' may be used uninitialized in this function [-Wmaybe-uninitialized]
  warning: 'm' may be used uninitialized in this function [-Wmaybe-uninitialized]

Tested using gcc version 4.7.3.

Signed-off-by: Sylvain Lemieux 
[sboyd@codeaurora.org: Drop assignment of hw to NULL as return
silences it and is less likely to lead to hiding problems later]
Signed-off-by: Stephen Boyd

clk: nxp: Remove CLK_IS_ROOT

2016-03-03T01:45:22+00:00

This flag is a no-op now. Remove usage of the flag.

Acked-by: Joachim Eastwood 
Signed-off-by: Stephen Boyd

clk: lpc32xx: add HCLK PLL output configuration

2016-02-10T20:45:16+00:00

This patch add the support to setup the HCLK PLL output
using the "assigned-clock-rates" parameter in the device tree.

If the option is not use, the clock setup by the kickstart
and/or bootloader remain unchanged.

The previous kernel version did not change the clock frequency
output setup by the kickstart and/or bootloader;
this version always setup the clock frequency output to 208MHz.

Signed-off-by: Sylvain Lemieux 
Signed-off-by: Stephen Boyd

clk: lpc32xx: do not register clock "0"

2016-02-10T00:19:34+00:00

The following errors are display in the console during the power-on:
[    0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12
[    0.000000] lpc32xx_clk_init: failed to register (null) clock: -12

There is no need to register clock "0"; the first clock used is 1;

Signed-off-by: Sylvain Lemieux 
Acked-by: Vladimir Zapolskiy 
[sboyd@codeaurora.org: s/prepare/register/]
Signed-off-by: Stephen Boyd

clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h

2016-01-29T20:59:50+00:00

to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.

Signed-off-by: Geliang Tang 
Signed-off-by: Stephen Boyd

clk-divider: make sure read-only dividers do not write to their register

2016-01-29T20:44:37+00:00

Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed
the special ops struct for read-only clocks and instead opted to handle
them inside the regular ops.

On the rk3368 this results in breakage as aclkm now gets set a value.
While it is the same divider value, the A53 core still doesn't like it,
which can result in the cpu ending up in a hang.
The reason being that "ACLKENMasserts one clock cycle before the rising
edge of ACLKM" and the clock should only be touched when STANDBYWFIL2
is asserted.

To fix this, reintroduce the read-only ops but do include the round_rate
callback. That way no writes that may be unsafe are done to the divider
register in any case.

The Rockchip use of the clk_divider_ops is adapted to this split again,
as is the nxp, lpc18xx-ccu driver that was included since the original
commit. On lpc18xx-ccu the divider seems to always be read-only
so only uses the new ops now.

Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1")
Reported-by: Zhang Qing 
Signed-off-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd

clk: lpc32xx: add common clock framework driver

2015-12-24T20:31:26+00:00

Add support for all configurable clocks found on NXP LPC32xx SoC.

The list contains several heterogenous groups of clocks:
* system clocks including multiple dividers and muxes,
* x397 PLL, HCLK PLL and USB PLL,
* peripheral clocks inherited from rtc, hclk and pclk,
* USB controller clocks: AHB slave, I2C, OTG, OHCI and device.

Signed-off-by: Vladimir Zapolskiy 
Signed-off-by: Michael Turquette

clk: lpc18xx-cgu: fix potential system hang when disabling unused clocks

2015-10-26T19:36:58+00:00

The clock consumer (CCU) of the CGU must be able to check if a CGU
base clock is really running since access to the CCU registers
requires a running base clock. Access with a disabled base clock will
cause the system to hang. Fix this issue by adding code that check if
the parent clock is running in the is_enabled clk_ops callback. Since
certain clocks can be cascaded this must be added to all clock gates.

The hang would occur if the boot ROM or boot loader didn't setup and
enable the USB0 clock. Then when the clk framework tried to access
the CCU register it would hang the system.

Signed-off-by: Joachim Eastwood 
Signed-off-by: Stephen Boyd

clk: lpc18xx-ccu: fix potential system hang when disabling unused clocks

2015-10-26T19:36:56+00:00

CCU branch clock register must only be accessed while the base
(parent) clock is running. Access with a disabled base clock
will cause the system to hang. Fix this issue by adding code
that check if the parent clock is running in the is_enabled
clk_ops callback.

This hang would occur when disabling unused clocks after AMBA
runtime pm had already disabled some of the clocks.

Signed-off-by: Joachim Eastwood 
Signed-off-by: Stephen Boyd