linux-stable.git/drivers/clk/microchip, branch v6.0

clk: microchip: mpfs: make the rtc's ahb clock critical

2022-09-14T07:45:52+00:00

The onboard RTC's AHB bus clock must be kept running as the RTC will
stop & lose track of time if the AHB interface clock is disabled.

Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
Signed-off-by: Conor Dooley 
Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/20220909123123.2699583-3-conor.dooley@microchip.com

clk: microchip: mpfs: fix clk_cfg array bounds violation

2022-09-14T07:45:51+00:00

There is an array bounds violation present during clock registration,
triggered by current code by only specific toolchains. This seems to
fail gracefully in v6.0-rc1, using a toolchain build from the riscv-
gnu-toolchain repo and with clang-15, and life carries on. While
converting the driver to use standard clock structs/ops, kernel panics
were seen during boot when built with clang-15:

[    0.581754] Unable to handle kernel NULL pointer dereference at virtual address 00000000000000b1
[    0.591520] Oops [#1]
[    0.594045] Modules linked in:
[    0.597435] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.0.0-rc1-00011-g8e1459cf4eca #1
[    0.606188] Hardware name: Microchip PolarFire-SoC Icicle Kit (DT)
[    0.613012] epc : __clk_register+0x4a6/0x85c
[    0.617759]  ra : __clk_register+0x49e/0x85c
[    0.622489] epc : ffffffff803faf7c ra : ffffffff803faf74 sp : ffffffc80400b720
[    0.630466]  gp : ffffffff810e93f8 tp : ffffffe77fe60000 t0 : ffffffe77ffb3800
[    0.638443]  t1 : 000000000000000a t2 : ffffffffffffffff s0 : ffffffc80400b7c0
[    0.646420]  s1 : 0000000000000001 a0 : 0000000000000001 a1 : 0000000000000000
[    0.654396]  a2 : 0000000000000001 a3 : 0000000000000000 a4 : 0000000000000000
[    0.662373]  a5 : ffffffff803a5810 a6 : 0000000200000022 a7 : 0000000000000006
[    0.670350]  s2 : ffffffff81099d48 s3 : ffffffff80d6e28e s4 : 0000000000000028
[    0.678327]  s5 : ffffffff810ed3c8 s6 : ffffffff810ed3d0 s7 : ffffffe77ffbc100
[    0.686304]  s8 : ffffffe77ffb1540 s9 : ffffffe77ffb1540 s10: 0000000000000008
[    0.694281]  s11: 0000000000000000 t3 : 00000000000000c6 t4 : 0000000000000007
[    0.702258]  t5 : ffffffff810c78c0 t6 : ffffffe77ff88cd0
[    0.708125] status: 0000000200000120 badaddr: 00000000000000b1 cause: 000000000000000d
[    0.716869] [] devm_clk_hw_register+0x62/0xaa
[    0.723420] [] mpfs_clk_probe+0x1e0/0x244

In v6.0-rc1 and later, this issue is visible without the follow on
patches doing the conversion using toolchains provided by our Yocto
meta layer too.

It fails on "clk_periph_timer" - which uses a different parent, that it
tries to find using the macro:
\#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].cfg.hw)

If parent is RTCREF, so the macro becomes: &mpfs_cfg_clks[33].cfg.hw
which is well beyond the end of the array. Amazingly, builds with GCC
11.1 see no problem here, booting correctly and hooking the parent up
etc. Builds with clang-15 do not, with the above panic.

Change the macro to use specific offsets depending on the parent rather
than the dt-binding's clock IDs.

Fixes: 1c6a7ea32b8c ("clk: microchip: mpfs: add RTCREF clock control")
CC: Nathan Chancellor 
Signed-off-by: Conor Dooley 
Reviewed-by: Claudiu Beznea 
Signed-off-by: Claudiu Beznea 
Link: https://lore.kernel.org/r/20220909123123.2699583-2-conor.dooley@microchip.com

clk: microchip: mpfs: add RTCREF clock control

2022-04-23T01:40:26+00:00

The reference clock used by the PolarFire SoC's onboard rtc was missing
from the clock driver. Add this clock at the "config" clock level, with
the external reference clock as its parent.

Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
Reviewed-by: Daire McNamara 
Signed-off-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220413075835.3354193-9-conor.dooley@microchip.com
Acked-by: Palmer Dabbelt 
Signed-off-by: Stephen Boyd

clk: microchip: mpfs: re-parent the configurable clocks

2022-04-23T01:40:22+00:00

Currently the mpfs clock driver uses a reference clock called the
"msspll", set in the device tree, as the parent for the cpu/axi/ahb
(config) clocks. The frequency of the msspll is determined by the FPGA
bitstream & the bootloader configures the clock to match the bitstream.
The real reference is provided by a 100 or 125 MHz off chip oscillator.

However, the msspll clock is not actually the parent of all clocks on
the system - the reference clock for the rtc/mtimer actually has the
off chip oscillator as its parent.

In order to fix this, add support for reading the configuration of the
msspll & reparent the "config" clocks so that they are derived from
this clock rather than the reference in the device tree.

Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
Reviewed-by: Daire McNamara 
Signed-off-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220413075835.3354193-8-conor.dooley@microchip.com
Acked-by: Palmer Dabbelt 
Signed-off-by: Stephen Boyd

clk: microchip: mpfs: mark CLK_ATHENA as critical

2022-04-23T01:40:04+00:00

CLK_ATHENA is another fabric interconnect and should be marked as critical
as with FIC0-3, since disabling it will cause part of the fabric to go
into reset.

Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
Reviewed-by: Daire McNamara 
Signed-off-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220413075835.3354193-3-conor.dooley@microchip.com
Acked-by: Palmer Dabbelt 
Signed-off-by: Stephen Boyd

clk: microchip: mpfs: fix parents for FIC clocks

2022-04-23T01:39:59+00:00

The fabric interconnects are on the AXI bus not AHB.
Update their parent clocks to fix this.

Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
Reviewed-by: Daire McNamara 
Signed-off-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220413075835.3354193-2-conor.dooley@microchip.com
Acked-by: Palmer Dabbelt 
Signed-off-by: Stephen Boyd

clk: microchip: mpfs: don't reset disabled peripherals

2022-04-22T02:35:07+00:00

The current clock driver for PolarFire SoC puts the hardware behind
"periph" clocks into reset if their clock is disabled. CONFIG_PM was
recently added to the riscv defconfig and exposed issues caused by this
behaviour, where the Cadence GEM was being put into reset between its
bringup & the PHY bringup:

https://lore.kernel.org/linux-riscv/9f4b057d-1985-5fd3-65c0-f944161c7792@microchip.com/

Fix this (for now) by removing the reset from mpfs_periph_clk_disable.

Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC")
Reviewed-by: Daire McNamara 
Signed-off-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220411072340.740981-1-conor.dooley@microchip.com
Signed-off-by: Stephen Boyd

clk: microchip: Add driver for Microchip PolarFire SoC

2022-03-12T03:31:52+00:00

Add support for clock configuration on Microchip PolarFire SoC

Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Co-developed-by: Padmarao Begari 
Signed-off-by: Padmarao Begari 
Signed-off-by: Daire McNamara 
Co-developed-by: Conor Dooley 
Signed-off-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220222121143.3316880-2-conor.dooley@microchip.com
Signed-off-by: Stephen Boyd

clk: let init callback return an error code

2019-12-24T02:53:13+00:00

If the init callback is allowed to request resources, it needs a return
value to report the outcome of such a request.

Signed-off-by: Jerome Brunet 
Link: https://lkml.kernel.org/r/20190924123954.31561-3-jbrunet@baylibre.com
Reviewed-by: Andrew Lunn 
Acked-by: Heiko Stuebner 
Signed-off-by: Stephen Boyd

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 445

2019-06-05T15:37:18+00:00

Based on 1 normalized pattern(s):

  this program is free software you can distribute it and or modify it
  under the terms of the gnu general public license version 2 as
  published by the free software foundation this program is
  distributed in the hope it will be useful but without any warranty
  without even the implied warranty of merchantability or fitness for
  a particular purpose see the gnu general public license for more
  details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 24 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Armijn Hemel 
Reviewed-by: Allison Randal 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.872212424@linutronix.de
Signed-off-by: Greg Kroah-Hartman