linux-stable.git/drivers/clk/meson, branch v6.2

Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-ti' into clk-next

2022-12-12T19:12:52+00:00

* clk-bindings:
  dt-bindings: clock: ti,cdce925: Convert to DT schema

* clk-renesas: (26 commits)
  clk: renesas: r8a779f0: Fix Ethernet Switch clocks
  clk: renesas: r8a779g0: Add Z0 clock support
  clk: renesas: r8a779g0: Add CMT clocks
  clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks
  clk: renesas: r8a779f0: Fix SCIF parent clocks
  clk: renesas: r8a779f0: Fix HSCIF parent clocks
  clk: renesas: r9a06g032: Repair grave increment error
  clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM
  clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc
  clk: renesas: r8a779a0: Fix SD0H clock name
  clk: renesas: r8a779g0: Add RPC-IF clock
  clk: renesas: r8a779g0: Add SDHI clocks
  clk: renesas: r8a779f0: Add SASYNCPER internal clock
  clk: renesas: r8a779f0: Fix SD0H clock name
  clk: renesas: r9a07g043: Drop WDT2 clock and reset entry
  clk: renesas: r9a07g044: Drop WDT2 clock and reset entry
  clk: renesas: r8a779g0: Add TPU clock
  clk: renesas: r8a779g0: Add PWM clock
  clk: renesas: r8a779g0: Add SCIF clocks
  clk: renesas: r9a07g044: Add MTU3a clock and reset entry
  ...

* clk-amlogic:
  clk: meson: pll: add pcie lock retry workaround
  clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()

* clk-allwinner:
  clk: sunxi-ng: f1c100s: Add IR mod clock
  clk: sunxi-ng: v3s: Correct the header guard of ccu-sun8i-v3s.h

* clk-ti:
  clk: ti: fix typo in ti_clk_retry_init() code comment
  clk: ti: dra7-atl: don't allocate `parent_names' variable
  clk: ti: change ti_clk_register[_omap_hw]() API

clk: Remove a useless include

2022-11-23T01:52:07+00:00

 is not needed for these drivers. Remove the
corresponding #include.

Signed-off-by: Christophe JAILLET 
Link: https://lore.kernel.org/r/12dd5cb49efa7714f8e0389e4c7b3bc829e8a90e.1668289299.git.christophe.jaillet@wanadoo.fr
Acked-by: Heiko Stuebner 
Acked-by: Jerome Brunet 
Reviewed-by: Luca Ceresoli 
Signed-off-by: Stephen Boyd

clk: meson: pll: add pcie lock retry workaround

2022-11-08T16:05:02+00:00

The PCIe PLL locking may be unreliable under some circumstance, such as
high or low temperature. If the PLL fails to lock, reset it a try again.

This helps on the S905X4

Signed-off-by: Heiner Kallweit 
[commit message amend]
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/cc80cda0-4dda-2e3e-3fc8-afa97717479b@gmail.com

clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()

2022-11-08T16:05:02+00:00

Currently we loop over meson_parm_read() up to 24mln times.
This results in a unpredictable timeout period. In my case
it's over 5s on a S905X4-based system. Make the timeout
period predictable and set it to 100ms.

Signed-off-by: Heiner Kallweit 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/a801afc0-a8f2-a0a4-0f2b-a7201351d563@gmail.com

clk: meson: Hold reference returned by of_get_parent()

2022-08-19T21:29:00+00:00

We should hold the reference returned by of_get_parent() and use it
to call of_node_put() for refcount balance.

Fixes: 88e2da81241e ("clk: meson: aoclk: refactor common code into dedicated file")
Fixes: 6682bd4d443f ("clk: meson: factorise meson64 peripheral clock controller drivers")
Fixes: bb6eddd1d28c ("clk: meson: meson8b: use the HHI syscon if available")

Signed-off-by: Liang He 
Link: https://lore.kernel.org/r/20220628141038.168383-1-windhl@126.com
Reviewed-by: Neil Armstrong 
Reviewed-by: Martin Blumenstingl 
Signed-off-by: Stephen Boyd

clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()

2022-06-16T02:22:29+00:00

The clk API just got a function with a slightly different name and
the same functionality. Remove the duplication.

Signed-off-by: Uwe Kleine-König 
Link: https://lore.kernel.org/r/20220520075737.758761-5-u.kleine-koenig@pengutronix.de
Signed-off-by: Stephen Boyd

clk: cleanup comments

2022-03-12T02:22:15+00:00

For spdx
Space instead of tab before spdx tag

Removed repeated works
the, to, two

Replacements
much much to a much
'to to' to 'to do'
aready to already
Comunications to Communications
freqency to frequency

Signed-off-by: Tom Rix 
Link: https://lore.kernel.org/r/20220222195153.3817625-1-trix@redhat.com
Signed-off-by: Stephen Boyd

clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB

2021-11-30T09:28:52+00:00

There are reports that 48kHz audio does not work on the WeTek Play 2
(which uses a GXBB SoC), while 44.1kHz audio works fine on the same
board. There are also reports of 48kHz audio working fine on GXL and
GXM SoCs, which are using an (almost) identical AIU (audio controller).

Experimenting has shown that MPLL0 is causing this problem. In the .dts
we have by default:
	assigned-clocks = <&clkc CLKID_MPLL0>,
			  <&clkc CLKID_MPLL1>,
			  <&clkc CLKID_MPLL2>;
	assigned-clock-rates = <294912000>,
			       <270950400>,
			       <393216000>;
The MPLL0 rate is divisible by 48kHz without remainder and the MPLL1
rate is divisible by 44.1kHz without remainder. Swapping these two clock
rates "fixes" 48kHz audio but breaks 44.1kHz audio.

Everything looks normal when looking at the info provided by the common
clock framework while playing 48kHz audio (via I2S with mclk-fs = 256):
        mpll_prediv                 1        1        0  2000000000
           mpll0_div                1        1        0   294909641
              mpll0                 1        1        0   294909641
                 cts_amclk_sel       1        1        0   294909641
                    cts_amclk_div       1        1        0    12287902
                       cts_amclk       1        1        0    12287902

meson-clk-msr however shows that the actual MPLL0 clock is off by more
than 38MHz:
        mp0_out               333322917    +/-10416Hz

The rate seen by meson-clk-msr is very close to what we would get when
SDM (the fractional part) was ignored:
  (2000000000Hz * 16384) / ((16384 * 6) = 333.33MHz
If SDM was considered the we should get close to:
  (2000000000Hz * 16384) / ((16384 * 6) + 12808) = 294.9MHz

Further experimenting shows that HHI_MPLL_CNTL7[15] does not have any
effect on the rate of MPLL0 as seen my meson-clk-msr (regardless of
whether that bit is zero or one the rate is always the same according to
meson-clk-msr). Using HHI_MPLL_CNTL[25] on the other hand as SDM_EN
results in SDM being considered for the rate output by the hardware. The
rate - as seen by meson-clk-msr - matches with what we expect when
SDM_EN is enabled (fractional part is being considered, resulting in a
294.9MHz output) or disable (fractional part being ignored, resulting in
a 333.33MHz output).

Reported-by: Christian Hewitt 
Tested-by: Christian Hewitt 
Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20211031135006.1508796-1-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Make the video clock trees mutable

2021-09-23T09:46:38+00:00

Switch from the "_ro" clock op variants to the mutable ones for all
video clocks. This will allow the VPU driver to change the clocks as
needed for the different video output modes.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20210713232510.3057750-6-martin.blumenstingl@googlemail.com

clk: meson: meson8b: Initialize the HDMI PLL registers

2021-09-23T09:46:37+00:00

Add the reg_sequence to initialize the HDMI PLL with the settings for
a video mode that doesn't require PLL internal clock doubling. These
settings are taken from the 3.10 vendor kernel's driver for the 2970MHz
PLL setting used for the 1080P video mode. This puts the PLL into a
defined state and the Linux kernel can take over.
While not all bits for this PLL are implemented using these "defaults"
and then applying M, N and FRAC seems to work fine.

Signed-off-by: Martin Blumenstingl 
Signed-off-by: Jerome Brunet 
Link: https://lore.kernel.org/r/20210713232510.3057750-5-martin.blumenstingl@googlemail.com