linux-stable.git/drivers/clk/meson, branch linux-5.0.y Linux kernel stable tree clk: meson-gxbb: round the vdec dividers to closest 2019-05-10T16:36:06+00:00 Maxime Jourdan mjourdan@baylibre.com 2019-03-19T10:25:37+00:00 5bff91d2a18faaa1f29d3056cd49bf1988813ac1 [ Upstream commit 9b70c697e87286ade406e6a02091757307dd4b7c ] We want the video decoder clocks to always round to closest. While the muxes are already using CLK_MUX_ROUND_CLOSEST, the corresponding CLK_DIVIDER_ROUND_CLOSEST was forgotten for the dividers. Fix this by adding the flag to the two vdec dividers. Fixes: a565242eb9fc ("clk: meson: gxbb: add the video decoder clocks") Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190319102537.2043-1-mjourdan@baylibre.com Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit 9b70c697e87286ade406e6a02091757307dd4b7c ]

We want the video decoder clocks to always round to closest. While the
muxes are already using CLK_MUX_ROUND_CLOSEST, the corresponding
CLK_DIVIDER_ROUND_CLOSEST was forgotten for the dividers.

Fix this by adding the flag to the two vdec dividers.

Fixes: a565242eb9fc ("clk: meson: gxbb: add the video decoder clocks")
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190319102537.2043-1-mjourdan@baylibre.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Revert "clk: meson: clean-up clock registration" 2019-04-17T06:39:45+00:00 Neil Armstrong narmstrong@baylibre.com 2019-04-11T10:11:32+00:00 e2a0237494ce1181d2b5002280a06b553ad54fdf This reverts commit 9b0f430450cf230e736bc40f95bf34fbdb99cead. This patch was not initially a fix and is dependent on other changes which are not fixes eithers. With this change, multiple Amlogic based boards fails to boot, as reported by kernelci. Cc: stable@vger.kernel.org # 5.0.7 Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 
This reverts commit 9b0f430450cf230e736bc40f95bf34fbdb99cead.

This patch was not initially a fix and is dependent on other
changes which are not fixes eithers.

With this change, multiple Amlogic based boards fails to boot,
as reported by kernelci.

Cc: stable@vger.kernel.org # 5.0.7
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
clk: meson: clean-up clock registration 2019-04-05T20:34:52+00:00 Jerome Brunet jbrunet@baylibre.com 2018-12-21T16:02:36+00:00 9b0f430450cf230e736bc40f95bf34fbdb99cead [ Upstream commit 8d9981efbcab066d17af4d3c85c169200f6f78df ] Order, ids and size between the table of regmap clocks and the onecell data table could be different. Set regmap pointer in all the regmap clocks before starting the registration using the onecell data, to make sure we don't get into an incoherent situation. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181221160239.26265-3-jbrunet@baylibre.com Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit 8d9981efbcab066d17af4d3c85c169200f6f78df ]

Order, ids and size  between the table of regmap clocks and the onecell
data table could be different.

Set regmap pointer in all the regmap clocks before starting the
registration using the onecell data, to make sure we don't
get into an incoherent situation.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181221160239.26265-3-jbrunet@baylibre.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Merge branch 'clk-fixes' into clk-next 2018-12-14T21:42:08+00:00 Stephen Boyd sboyd@kernel.org 2018-12-14T21:42:08+00:00 9dc320424708378b7a2137a148fc4fc816105ba2 * clk-fixes: clk: qcom: qcs404: Fix gpll0_out_main parent clk: zynqmp: Off by one in zynqmp_is_valid_clock() clk: mmp: Off by one in mmp_clk_add() clk: mvebu: Off by one bugs in cp110_of_clk_get() arm64: dts: qcom: sdm845-mtp: Mark protected gcc clocks clk: zynqmp: handle fixed factor param query error clk: qcom: gcc: Fix board clock node name clk: meson: axg: mark fdiv2 and fdiv3 as critical clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL clk: fixed-factor: fix of_node_get-put imbalance 
* clk-fixes:
  clk: qcom: qcs404: Fix gpll0_out_main parent
  clk: zynqmp: Off by one in zynqmp_is_valid_clock()
  clk: mmp: Off by one in mmp_clk_add()
  clk: mvebu: Off by one bugs in cp110_of_clk_get()
  arm64: dts: qcom: sdm845-mtp: Mark protected gcc clocks
  clk: zynqmp: handle fixed factor param query error
  clk: qcom: gcc: Fix board clock node name
  clk: meson: axg: mark fdiv2 and fdiv3 as critical
  clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL
  clk: fixed-factor: fix of_node_get-put imbalance
Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into clk-meson 2018-12-13T09:05:44+00:00 Stephen Boyd sboyd@kernel.org 2018-12-13T09:05:44+00:00 e74581b79ddd9b49b8c61e2791fc4dffc0245afb Pull more meson clk driver updates from Neil Armstrong: - Fix GXL HDMI Pll fractional bits (from first round) - Add the Meson8/Meson8b video clocks - Add clk-input helper and use it for axg-audio clock driver * tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson: clk: meson: axg-audio: use the clk input helper function clk: meson: add clk-input helper function clk: meson: meson8b: add the read-only video clock trees clk: meson: meson8b: add the fractional divider for vid_pll_dco clk: meson: meson8b: fix the offset of vid_pll_dco's N value clk: meson: Fix GXL HDMI PLL fractional bits width 
Pull more meson clk driver updates from Neil Armstrong:

 - Fix GXL HDMI Pll fractional bits (from first round)
 - Add the Meson8/Meson8b video clocks
 - Add clk-input helper and use it for axg-audio clock driver

* tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson:
  clk: meson: axg-audio: use the clk input helper function
  clk: meson: add clk-input helper function
  clk: meson: meson8b: add the read-only video clock trees
  clk: meson: meson8b: add the fractional divider for vid_pll_dco
  clk: meson: meson8b: fix the offset of vid_pll_dco's N value
  clk: meson: Fix GXL HDMI PLL fractional bits width
clk: meson: axg-audio: use the clk input helper function 2018-12-11T15:07:03+00:00 Jerome Brunet jbrunet@baylibre.com 2018-12-04T16:58:19+00:00 f03566d0aa79f9e09a288936980741c479a22fdb Rework the axg audio clock controller to use the new clk-input helper function. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: fixed pclk input clock name to axg_audio_pclk] Link: http://lkml.kernel.org/r/20181204165819.21541-3-jbrunet@baylibre.com 
Rework the axg audio clock controller to use the new clk-input helper
function.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: fixed pclk input clock name to axg_audio_pclk]
Link: http://lkml.kernel.org/r/20181204165819.21541-3-jbrunet@baylibre.com
clk: meson: add clk-input helper function 2018-12-05T10:24:40+00:00 Jerome Brunet jbrunet@baylibre.com 2018-12-04T16:58:18+00:00 e456e6a12b7ad49b6e8ce2edfd30782ed6985cfb Add the clock input helper function. Several amlogic clock controllers will now be registering bypass clock input. Instead of copying this code in every of them, let's make an helper function for it Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: fixed up to apply on Makefile and clkc.h] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181204165819.21541-2-jbrunet@baylibre.com 
Add the clock input helper function. Several amlogic clock controllers
will now be registering bypass clock input. Instead of copying this
code in every of them, let's make an helper function for it

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: fixed up to apply on Makefile and clkc.h]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181204165819.21541-2-jbrunet@baylibre.com
clk: meson: Mark some things static 2018-12-03T21:52:56+00:00 Stephen Boyd sboyd@kernel.org 2018-12-03T21:52:56+00:00 8913e8a73d03470b7aeaeab9c4f4fd3b50a0e2ec These are missing 'static' so sparse complains: drivers/clk/meson/vid-pll-div.c:58:26: warning: symbol '_get_table_val' was not declared. Should it be static? drivers/clk/meson/gxbb.c:1585:12: warning: symbol 'gxbb_vid_pll_parent_names' was not declared. Should it be static? drivers/clk/meson/gxbb.c:1620:12: warning: symbol 'gxbb_vclk_parent_names' was not declared. Should it be static? drivers/clk/meson/gxbb.c:1980:12: warning: symbol 'gxbb_cts_parent_names' was not declared. Should it be static? drivers/clk/meson/gxbb.c:2036:12: warning: symbol 'gxbb_cts_hdmi_tx_parent_names' was not declared. Should it be static? Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
These are missing 'static' so sparse complains:

drivers/clk/meson/vid-pll-div.c:58:26: warning: symbol '_get_table_val' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:1585:12: warning: symbol 'gxbb_vid_pll_parent_names' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:1620:12: warning: symbol 'gxbb_vclk_parent_names' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:1980:12: warning: symbol 'gxbb_cts_parent_names' was not declared. Should it be static?
drivers/clk/meson/gxbb.c:2036:12: warning: symbol 'gxbb_cts_hdmi_tx_parent_names' was not declared. Should it be static?

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: meson: meson8b: add the read-only video clock trees 2018-12-03T10:50:06+00:00 Martin Blumenstingl martin.blumenstingl@googlemail.com 2018-12-02T21:42:20+00:00 6cb57c678bb70ea180362ac47a5bf78a8c579b45 Add all clocks to give us the final video clocks within the Meson8, Meson8b and Meson8m2 SoCs. The final video clocks are: - cts_enct - cts_encl - cts_encp - cts_enci - cts_vdac0 - hdmi_tx_pixel - hdmi_sys Add multiple clocks in between which are needed to implement these clocks: - Opposed to GXBB there is no pre-multiplier for the PLL input. The assumption here is that the multiplier is required to achieve the HDMI 2.0 clock rates (which are up to twice the rate of the HDMI 1.4 rates). - The main PLL is called "HDMI PLL" or "HPLL" in the datasheet. Rename our existing "vid_pll_dco" to "hdmi_pll_dco". The actual VID_PLL clock also exists further down the tree. - Rename the existing "vid_pll" clock (which is the OD divider at HHI_VID_PLL_CNTL[17:16]) to "hdmi_pll_lvds_out" to match the naming from the datasheet. - Add the second OD divider called "hdmi_pll_hdmi_out" at HHI_VID_PLL_CNTL[19:18]. - Add the "vid_pll_in_sel" which can choose between "hdmi_pll_dco" and another parent. However, the second parent is not use on Amlogic's 3.10 kernel for HDMI or CVBS output so just leave a TODO in the code. - Add the "vid_pll_in_en" which is located after "vid_pll_in_sel" according to the datasheet. - Add "vid_pll_pre_div" which is used for divide-by-5 and divide-by-6 in Amlogic's 3.10 kernel sources. - Add "vid_pll_post_div" which divides the output of "vid_pll_pre_div" further down. The Amlogic 3.10 kernel configures this as divide-by-2 with "vid_pll_pre_div" being configured as divide-by-5 to achieve a total divider of 10. - Add the real "vid_pll" clock which selects between "vid_pll_pre_div", "vid_pll_post_div" and a third "vid_pll_pre_div_mult7_div2" (which is "vid_pll_pre_div" divided by 3.5). The latter is not supported yet because it's not used in Amlogic's 3.10 kernel. The "vid_pll" clock rate can also be measured by clkmsr to check whether this implementation is correct. - Add "vid_pll_final_div" which is a post-divider for "vid_pll" and it's used as input for "vclk" and "vclk2" - Add the two symmetric "vclk" and "vclk" clock trees, each with a divide-by-1, divide-by-2, divide-by-4, divide-by-6 and divide-by-12 clock and a divider for each clock. - Add the "cts_enct", "cts_encp" and "hdmi_tx_pixel" clocks which each have their own gate and can select between any of the five "vclk" dividers. - Add the "cts_encl" and "cts_vdac0" clocks which each have their own gate and can select between any of the five "vclk2" dividers. The "hdmi_sys" clock is a different than these video clocks. It takes "xtal" as input (there are three more but unknown parents). Add this clock as well as it's used by the HDMI controller. Amlogic's 3.10 kernel always configures this as "xtal divided by 1", so we can ignore the other parents for now. This was tested on Meson8b and Meson8m2 boards by comparing the common clock framework output with the clock measurer output. The following video modes were first set in u-boot (by running "video dev open $mode") before booting Linux: 4K2K30HZ (only supported by Meson8m2, not tested on Meson8b): - vid_pll: 297000000Hz - cts_encp: 297000000Hz - hdmi_tx_pixel: 297000000Hz 1080P: - vid_pll: 148500000Hz - cts_encp: 148500000Hz - hdmi_tx_pixel: 148500000Hz 720P: - vid_pll: 148500000Hz - cts_encp: 148500000Hz - hdmi_tx_pixel: 74250000Hz 480P: - vid_pll: 216000000Hz - cts_encp: 54000000Hz - hdmi_tx_pixel: 27000000Hz Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181202214220.7715-4-martin.blumenstingl@googlemail.com 
Add all clocks to give us the final video clocks within the Meson8,
Meson8b and Meson8m2 SoCs. The final video clocks are:
- cts_enct
- cts_encl
- cts_encp
- cts_enci
- cts_vdac0
- hdmi_tx_pixel
- hdmi_sys

Add multiple clocks in between which are needed to implement these
clocks:
- Opposed to GXBB there is no pre-multiplier for the PLL input. The
  assumption here is that the multiplier is required to achieve the HDMI
  2.0 clock rates (which are up to twice the rate of the HDMI 1.4
  rates).
- The main PLL is called "HDMI PLL" or "HPLL" in the datasheet. Rename
  our existing "vid_pll_dco" to "hdmi_pll_dco". The actual VID_PLL clock
  also exists further down the tree.
- Rename the existing "vid_pll" clock (which is the OD divider at
  HHI_VID_PLL_CNTL[17:16]) to "hdmi_pll_lvds_out" to match the naming
  from the datasheet.
- Add the second OD divider called "hdmi_pll_hdmi_out" at
  HHI_VID_PLL_CNTL[19:18].
- Add the "vid_pll_in_sel" which can choose between "hdmi_pll_dco" and
  another parent. However, the second parent is not use on Amlogic's
  3.10 kernel for HDMI or CVBS output so just leave a TODO in the code.
- Add the "vid_pll_in_en" which is located after "vid_pll_in_sel"
  according to the datasheet.
- Add "vid_pll_pre_div" which is used for divide-by-5 and divide-by-6 in
  Amlogic's 3.10 kernel sources.
- Add "vid_pll_post_div" which divides the output of "vid_pll_pre_div"
  further down. The Amlogic 3.10 kernel configures this as divide-by-2
  with "vid_pll_pre_div" being configured as divide-by-5 to achieve a
  total divider of 10.
- Add the real "vid_pll" clock which selects between "vid_pll_pre_div",
  "vid_pll_post_div" and a third "vid_pll_pre_div_mult7_div2" (which is
  "vid_pll_pre_div" divided by 3.5). The latter is not supported yet
  because it's not used in Amlogic's 3.10 kernel. The "vid_pll" clock
  rate can also be measured by clkmsr to check whether this
  implementation is correct.
- Add "vid_pll_final_div" which is a post-divider for "vid_pll" and it's
  used as input for "vclk" and "vclk2"
- Add the two symmetric "vclk" and "vclk" clock trees, each with a
  divide-by-1, divide-by-2, divide-by-4, divide-by-6 and divide-by-12
  clock and a divider for each clock.
- Add the "cts_enct", "cts_encp" and "hdmi_tx_pixel" clocks which each
  have their own gate and can select between any of the five "vclk"
  dividers.
- Add the "cts_encl" and "cts_vdac0" clocks which each have their own
  gate and can select between any of the five "vclk2" dividers.

The "hdmi_sys" clock is a different than these video clocks. It takes
"xtal" as input (there are three more but unknown parents). Add this
clock as well as it's used by the HDMI controller. Amlogic's 3.10 kernel
always configures this as "xtal divided by 1", so we can ignore the
other parents for now.

This was tested on Meson8b and Meson8m2 boards by comparing the common
clock framework output with the clock measurer output. The following
video modes were first set in u-boot (by running "video dev open $mode")
before booting Linux:
4K2K30HZ (only supported by Meson8m2, not tested on Meson8b):
- vid_pll: 297000000Hz
- cts_encp: 297000000Hz
- hdmi_tx_pixel: 297000000Hz
1080P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 148500000Hz
720P:
- vid_pll: 148500000Hz
- cts_encp: 148500000Hz
- hdmi_tx_pixel: 74250000Hz
480P:
- vid_pll: 216000000Hz
- cts_encp: 54000000Hz
- hdmi_tx_pixel: 27000000Hz

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-4-martin.blumenstingl@googlemail.com
clk: meson: meson8b: add the fractional divider for vid_pll_dco 2018-12-03T10:49:51+00:00 Martin Blumenstingl martin.blumenstingl@googlemail.com 2018-12-02T21:42:19+00:00 007f3da7d38ac7eb71fb092e43354dbf2e7b5109 This "vid_pll_dco" (which should be named HDMI_PLL or - as the datasheet calls it - HPLL) has a 12-bit wide fractional parameter at HHI_VID_PLL_CNTL2[11:0]. Add this so we correctly calculate the rate of this PLL when u-boot is configured for a video mode which uses this fractional parameter. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181202214220.7715-3-martin.blumenstingl@googlemail.com 
This "vid_pll_dco" (which should be named HDMI_PLL or - as the datasheet
calls it - HPLL) has a 12-bit wide fractional parameter at
HHI_VID_PLL_CNTL2[11:0]. Add this so we correctly calculate the rate of
this PLL when u-boot is configured for a video mode which uses this
fractional parameter.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-3-martin.blumenstingl@googlemail.com