linux-stable.git/drivers/clk/bcm, branch linux-4.6.y

clk: bcm2835: correctly enable fractional clock support

2016-06-08T01:23:38+00:00

commit 959ca92a3235fc4b17c1e18483fc390b3d612254 upstream.

The current driver calculates the clock divider with
fractional support enabled.

But it does not enable fractional support in the
control register itself resulting in an integer only divider,
but in clk_set_rate responds back the fractionally divided
clock frequency.

This patch enables fractional support in the control register
whenever there is a fractional bit set in the requested clock divider.

Mash clock limits are are also handled for the PWM clock
applying the correct divider limits (2 and max_int) applicable to
basic fractional divider support (mash order of 1).

It also adds locking to protect the read/modify/write cycle of
the register modification.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: divider value has to be 1 or more

2016-06-08T01:23:38+00:00

commit 997f16bd5d2e9b3456027f96fcadfe1e2bf12f4e upstream.

Current clamping of a normal divider allows a value < 1 to be valid.

A divider of < 1 would actually only be possible if we had a PLL...

So this patch clamps the divider to 1.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: pll_off should only update CM_PLL_ANARST

2016-06-08T01:23:38+00:00

commit 6727f086cfe4ddcc651eb2bf4301abfcf619be06 upstream.

bcm2835_pll_off is currently assigning CM_PLL_ANARST to the control
register, which may lose the other bits that are currently set by the
clock dividers.

It also now locks during the read/modify/write cycle of both
registers.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: Fix PLL poweron

2016-06-08T01:23:38+00:00

commit e708b383f4b94feca2e0d5d06e1cfc13cdfea100 upstream.

In poweroff, we set the reset bit and the power down bit, but only
managed to unset the reset bit for poweron.  This meant that if HDMI
did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the
PLLH (that had been on at boot time) and never recover.

Signed-off-by: Eric Anholt 
Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: add locking to pll*_on/off methods

2016-06-01T19:18:03+00:00

commit ec36a5c6682fdd5328abf15c3c67281bed0241d7 upstream.

Add missing locking to:
* bcm2835_pll_divider_on
* bcm2835_pll_divider_off
to protect the read modify write cycle for the
register access protecting both cm_reg and a2w_reg
registers.

Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the
audio domain clocks")

Signed-off-by: Martin Sperl 
Signed-off-by: Eric Anholt 
Reviewed-by: Eric Anholt 
Signed-off-by: Greg Kroah-Hartman

clk: bcm2835: fix check of error code returned by devm_ioremap_resource()

2016-03-16T01:14:11+00:00

The change fixes potential oops while accessing iomem on invalid
address, if devm_ioremap_resource() fails due to some reason.

The devm_ioremap_resource() function returns ERR_PTR() and never
returns NULL, which makes useless a following check for NULL.

Signed-off-by: Vladimir Zapolskiy 
Fixes: 5e63dcc74b30 ("clk: bcm2835: Add a driver for the auxiliary peripheral clock gates")
Reviewed-by: Eric Anholt 
Signed-off-by: Stephen Boyd

clk: bcm: Remove CLK_IS_ROOT

2016-03-03T01:42:41+00:00

This flag is a no-op now. Remove usage of the flag.

Cc: Lee Jones 
Reviewed-by: Eric Anholt 
Signed-off-by: Stephen Boyd

clk: bcm2835: added missing clock register definitions

2016-02-26T00:07:59+00:00

Added missing CTRL and DIV clock register definitions for:
PCM, SLIM, TCNT, TEC, TD0, TD1

Register information taken from:
https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM
which extracted the information from the header files shared by
Broadcom/rpi foundation in this file:
http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz

Signed-off-by: Martin Sperl 
Reviewed-by: Eric Anholt 
Signed-off-by: Stephen Boyd

Merge branch 'clk-bcm2835' into clk-next

2016-02-16T20:31:51+00:00

clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()

2016-02-16T20:30:09+00:00

We were rolling this ourselves, but clk-divider can do it now.

Signed-off-by: Eric Anholt 
Signed-off-by: Michael Turquette