<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/drivers/clk/Makefile, branch linux-4.8.y</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>clk: Makefile: re-sort and clean up</title>
<updated>2016-07-19T16:53:52+00:00</updated>
<author>
<name>Michael Turquette</name>
<email>mturquette@baylibre.com</email>
</author>
<published>2016-06-16T00:09:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=b328d2c110ad7b45af9cde2bce70803df28e9553'/>
<id>b328d2c110ad7b45af9cde2bce70803df28e9553</id>
<content type='text'>
Sorting is hard.

Signed-off-by: Michael Turquette &lt;mturquette@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Sorting is hard.

Signed-off-by: Michael Turquette &lt;mturquette@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'clk-sunxi-ng' into clk-next</title>
<updated>2016-07-09T01:08:56+00:00</updated>
<author>
<name>Michael Turquette</name>
<email>mturquette@baylibre.com</email>
</author>
<published>2016-07-09T01:08:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=7adb76956189d10fd77f00b41b4d413480e94715'/>
<id>7adb76956189d10fd77f00b41b4d413480e94715</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: sunxi-ng: Add common infrastructure</title>
<updated>2016-07-09T01:04:32+00:00</updated>
<author>
<name>Maxime Ripard</name>
<email>maxime.ripard@free-electrons.com</email>
</author>
<published>2016-06-29T19:05:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=1d80c14248d6082c91a8a9e3d70cc94c3cc18ecb'/>
<id>1d80c14248d6082c91a8a9e3d70cc94c3cc18ecb</id>
<content type='text'>
Start our new clock infrastructure by adding the registration code, common
structure and common code.

Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Michael Turquette &lt;mturquette@baylibre.com&gt;
Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Start our new clock infrastructure by adding the registration code, common
structure and common code.

Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Michael Turquette &lt;mturquette@baylibre.com&gt;
Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: meson: only build selected platforms</title>
<updated>2016-06-23T01:02:52+00:00</updated>
<author>
<name>Michael Turquette</name>
<email>mturquette@baylibre.com</email>
</author>
<published>2016-05-23T21:29:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=cb7c47d7066ca9fda053f5cb327ea49e14f42409'/>
<id>cb7c47d7066ca9fda053f5cb327ea49e14f42409</id>
<content type='text'>
Break the AmLogic clock code up so that only the necessary parts are
compiled and linked. The core code is selected by both arm and arm64
builds with COMMON_CLK_AMLOGIC. The individual drivers have their own
config options as well.

Tested-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
Signed-off-by: Michael Turquette &lt;mturquette@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Break the AmLogic clock code up so that only the necessary parts are
compiled and linked. The core code is selected by both arm and arm64
builds with COMMON_CLK_AMLOGIC. The individual drivers have their own
config options as well.

Tested-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
Signed-off-by: Michael Turquette &lt;mturquette@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux</title>
<updated>2016-05-21T03:18:12+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2016-05-21T03:18:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=0eff4589c36edd03d50b835d0768b2c2ef3f20bd'/>
<id>0eff4589c36edd03d50b835d0768b2c2ef3f20bd</id>
<content type='text'>
Pull clk updates from Stephen Boyd:
 "It's the usual big pile of driver updates and additions, but we do
  have a couple core changes in here as well.

  Core:

   - CLK_IS_CRITICAL support has been added.  This should allow drivers
     to properly express that a certain clk should stay on even if their
     prepare/enable count drops to 0 (and in turn the parents of these
     clks should stay enabled).

   - A clk registration API has been added, clk_hw_register(), and an OF
     clk provider API has been added, of_clk_add_hw_provider().  These
     APIs have been put in place to further split clk providers from clk
     consumers, with the goal being to have clk providers never deal
     with struct clk pointers at all.  Conversion of provider drivers is
     on going.  clkdev has also gained support for registering clk_hw
     pointers directly so we can convert drivers that don't use
     devicetree.

  New Drivers:

   - Marvell ap806 and cp110 system controllers (with clks inside!)
   - Hisilicon Hi3519 clock and reset controller
   - Axis ARTPEC-6 clock controllers
   - Oxford Semiconductor OXNAS clock controllers
   - AXS10X I2S PLL
   - Rockchip RK3399 clock and reset controller

  Updates:

   - MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos
     542x SoCs, and some more clk ID exporting for bus frequency scaling
   - Proper BCM2835 PCM clk support and various other clks
   - i.MX clk updates for i.MX6SX, i.MX7, and VF610
   - Renesas updates for R-Car H3
   - Tegra210 got updates for DisplayPort and HDMI 2.0
   - Rockchip driver refactorings and fixes due to adding RK3399 support"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits)
  clk: fix critical clock locking
  clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM
  clk: ingenic: Allow divider value to be divided
  clk: sunxi: Add display and TCON0 clocks driver
  clk: rockchip: drop old_rate calculation on pll rate changes
  clk: rockchip: simplify GRF handling in pll clocks
  clk: rockchip: lookup General Register Files in rockchip_clk_init
  clk: rockchip: fix the rk3399 sdmmc sample / drv name
  clk: mvebu: new driver for Armada CP110 system controller
  dt-bindings: arm: add DT binding for Marvell CP110 system controller
  clk: mvebu: new driver for Armada AP806 system controller
  clk: hisilicon: add CRG driver for hi3519 soc
  clk: hisilicon: export some hisilicon APIs to modules
  reset: hisilicon: add reset controller driver for hisilicon SOCs
  clk: bcm/kona: Do not use sizeof on pointer type
  clk: qcom: msm8916: Fix crypto clock flags
  clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0
  clk/axs10x: Add I2S PLL clock driver
  clk: imx7d: fix ahb clock mux 1
  clk: fix comment of devm_clk_hw_register()
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull clk updates from Stephen Boyd:
 "It's the usual big pile of driver updates and additions, but we do
  have a couple core changes in here as well.

  Core:

   - CLK_IS_CRITICAL support has been added.  This should allow drivers
     to properly express that a certain clk should stay on even if their
     prepare/enable count drops to 0 (and in turn the parents of these
     clks should stay enabled).

   - A clk registration API has been added, clk_hw_register(), and an OF
     clk provider API has been added, of_clk_add_hw_provider().  These
     APIs have been put in place to further split clk providers from clk
     consumers, with the goal being to have clk providers never deal
     with struct clk pointers at all.  Conversion of provider drivers is
     on going.  clkdev has also gained support for registering clk_hw
     pointers directly so we can convert drivers that don't use
     devicetree.

  New Drivers:

   - Marvell ap806 and cp110 system controllers (with clks inside!)
   - Hisilicon Hi3519 clock and reset controller
   - Axis ARTPEC-6 clock controllers
   - Oxford Semiconductor OXNAS clock controllers
   - AXS10X I2S PLL
   - Rockchip RK3399 clock and reset controller

  Updates:

   - MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos
     542x SoCs, and some more clk ID exporting for bus frequency scaling
   - Proper BCM2835 PCM clk support and various other clks
   - i.MX clk updates for i.MX6SX, i.MX7, and VF610
   - Renesas updates for R-Car H3
   - Tegra210 got updates for DisplayPort and HDMI 2.0
   - Rockchip driver refactorings and fixes due to adding RK3399 support"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits)
  clk: fix critical clock locking
  clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM
  clk: ingenic: Allow divider value to be divided
  clk: sunxi: Add display and TCON0 clocks driver
  clk: rockchip: drop old_rate calculation on pll rate changes
  clk: rockchip: simplify GRF handling in pll clocks
  clk: rockchip: lookup General Register Files in rockchip_clk_init
  clk: rockchip: fix the rk3399 sdmmc sample / drv name
  clk: mvebu: new driver for Armada CP110 system controller
  dt-bindings: arm: add DT binding for Marvell CP110 system controller
  clk: mvebu: new driver for Armada AP806 system controller
  clk: hisilicon: add CRG driver for hi3519 soc
  clk: hisilicon: export some hisilicon APIs to modules
  reset: hisilicon: add reset controller driver for hisilicon SOCs
  clk: bcm/kona: Do not use sizeof on pointer type
  clk: qcom: msm8916: Fix crypto clock flags
  clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0
  clk/axs10x: Add I2S PLL clock driver
  clk: imx7d: fix ahb clock mux 1
  clk: fix comment of devm_clk_hw_register()
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>CLK: microchip: Add Microchip PIC32 clock driver.</title>
<updated>2016-05-13T13:30:25+00:00</updated>
<author>
<name>Purna Chandra Mandal</name>
<email>purna.mandal@microchip.com</email>
</author>
<published>2016-05-13T07:52:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=ce6e1188465998820e7182455261b1f5d508ca17'/>
<id>ce6e1188465998820e7182455261b1f5d508ca17</id>
<content type='text'>
This clock driver implements PIC32 specific clock-tree. clock-tree
entities can only be configured through device-tree file (OF).

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Cc: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-clk@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13247/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This clock driver implements PIC32 specific clock-tree. clock-tree
entities can only be configured through device-tree file (OF).

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Cc: Michael Turquette &lt;mturquette@baylibre.com&gt;
Cc: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-clk@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13247/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk/axs10x: Add I2S PLL clock driver</title>
<updated>2016-05-06T17:35:04+00:00</updated>
<author>
<name>Jose Abreu</name>
<email>Jose.Abreu@synopsys.com</email>
</author>
<published>2016-05-02T09:39:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=923587aafc2c41ed516d39651d5750ea402cfc06'/>
<id>923587aafc2c41ed516d39651d5750ea402cfc06</id>
<content type='text'>
The ARC SDP I2S clock can be programmed using a
specific PLL.

This patch has the goal of adding a clock driver
that programs this PLL.

At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired rate.

Signed-off-by: Jose Abreu &lt;joabreu@synopsys.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The ARC SDP I2S clock can be programmed using a
specific PLL.

This patch has the goal of adding a clock driver
that programs this PLL.

At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired rate.

Signed-off-by: Jose Abreu &lt;joabreu@synopsys.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: Add Oxford Semiconductor OXNAS Standard Clocks</title>
<updated>2016-04-21T21:20:07+00:00</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2016-04-18T10:01:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=0bbd72b4c64fc0803a6efd86ea151184bf553f97'/>
<id>0bbd72b4c64fc0803a6efd86ea151184bf553f97</id>
<content type='text'>
Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
[sboyd@codeaurora.org: Drop NULL/continue check in registration
loop]
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
[sboyd@codeaurora.org: Drop NULL/continue check in registration
loop]
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'clk-artpec6' into clk-next</title>
<updated>2016-04-15T23:02:46+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2016-04-15T23:02:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=75ff88888093eddca478a8fa1b77b30edb4fa8be'/>
<id>75ff88888093eddca478a8fa1b77b30edb4fa8be</id>
<content type='text'>
* clk-artpec6:
  clk: add artpec-6 clock controller
  clk: add device tree binding for Artpec-6 clock controller
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* clk-artpec6:
  clk: add artpec-6 clock controller
  clk: add device tree binding for Artpec-6 clock controller
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: add artpec-6 clock controller</title>
<updated>2016-04-15T23:02:16+00:00</updated>
<author>
<name>Lars Persson</name>
<email>lars.persson@axis.com</email>
</author>
<published>2016-04-04T09:23:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=33b8ac917a8f7a22fa3d779f875646201d0097a0'/>
<id>33b8ac917a8f7a22fa3d779f875646201d0097a0</id>
<content type='text'>
Add a driver for the main clock controller of the Artpec-6 Soc.

Signed-off-by: Lars Persson &lt;larper@axis.com&gt;
[sboyd@codeaurora.org: Reformatted driver structure and of match]
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a driver for the main clock controller of the Artpec-6 Soc.

Signed-off-by: Lars Persson &lt;larper@axis.com&gt;
[sboyd@codeaurora.org: Reformatted driver structure and of match]
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
