linux-stable.git/arch, branch v3.14.44

ARM: fix missing syscall trace exit

2015-06-06T15:19:38+00:00

commit 1b97937246d8b97c0760d16d8992c7937bdf5e6a upstream.

Josh Stone reports:

  I've discovered a case where both arm and arm64 will miss a ptrace
  syscall-exit that they should report.  If the syscall is entered
  without TIF_SYSCALL_TRACE set, then it goes on the fast path.  It's
  then possible to have TIF_SYSCALL_TRACE added in the middle of the
  syscall, but ret_fast_syscall doesn't check this flag again.

Fix this by always checking for a syscall trace in the fast exit path.

Reported-by: Josh Stone 
Signed-off-by: Russell King 
Signed-off-by: Greg Kroah-Hartman

ARM: dts: imx27: only map 4 Kbyte for fec registers

2015-06-06T15:19:37+00:00

commit a29ef819f3f34f89a1b9b6a939b4c1cdfe1e85ce upstream.

According to the imx27 documentation, fec has a 4 Kbyte
memory space map. Moreover, the actual 16 Kbyte mapping
overlaps the SCC (Security Controller) memory register
space. So, we reduce the memory register space to 4 Kbyte.

Signed-off-by: Philippe Reynes 
Acked-by: Uwe Kleine-König 
Fixes: 9f0749e3eb88 ("ARM i.MX27: Add devicetree support")
Signed-off-by: Shawn Guo 
Signed-off-by: Greg Kroah-Hartman

crypto: s390/ghash - Fix incorrect ghash icv buffer handling.

2015-06-06T15:19:37+00:00

commit a1cae34e23b1293eccbcc8ee9b39298039c3952a upstream.

Multitheaded tests showed that the icv buffer in the current ghash
implementation is not handled correctly. A move of this working ghash
buffer value to the descriptor context fixed this. Code is tested and
verified with an multithreaded application via af_alg interface.

Signed-off-by: Harald Freudenberger 
Signed-off-by: Gerald Schaefer 
Reported-by: Herbert Xu 
Signed-off-by: Herbert Xu 
Signed-off-by: Greg Kroah-Hartman

powerpc: Align TOC to 256 bytes

2015-06-06T15:19:35+00:00

commit 5e95235ccd5442d4a4fe11ec4eb99ba1b7959368 upstream.

Recent toolchains force the TOC to be 256 byte aligned. We need
to enforce this alignment in our linker script, otherwise pointers
to our TOC variables (__toc_start, __prom_init_toc_start) could
be incorrect.

If they are bad, we die a few hundred instructions into boot.

Signed-off-by: Anton Blanchard 
Signed-off-by: Michael Ellerman 
Signed-off-by: Greg Kroah-Hartman

KVM: MMU: fix CR4.SMEP=1, CR0.WP=0 with shadow pages

2015-06-06T15:19:31+00:00

commit 898761158be7682082955e3efa4ad24725305fc7 upstream.

smep_andnot_wp is initialized in kvm_init_shadow_mmu and shadow pages
should not be reused for different values of it.  Thus, it has to be
added to the mask in kvm_mmu_pte_write.

Reviewed-by: Xiao Guangrong 
Signed-off-by: Paolo Bonzini 
Signed-off-by: Greg Kroah-Hartman

arm64: kvm: use inner-shareable barriers for inner-shareable maintenance

2015-05-17T16:53:52+00:00

commit ee9e101c11478680d579bd20bb38a4d3e2514fe3 upstream.

In order to ensure completion of inner-shareable maintenance instructions
(cache and TLB) on AArch64, we can use the -ish suffix to the dsb
instruction.

This patch relaxes our dsb sy instructions to dsb ish where possible.

Acked-by: Catalin Marinas 
Acked-by: Marc Zyngier 
Signed-off-by: Will Deacon 
Signed-off-by: Catalin Marinas 
Cc: Shannon Zhao 
Signed-off-by: Greg Kroah-Hartman

ARM: KVM: trap VM system registers until MMU and caches are ON

2015-05-17T16:53:52+00:00

commit 8034699a42d68043b495c7e0cfafccd920707ec8 upstream.

In order to be able to detect the point where the guest enables
its MMU and caches, trap all the VM related system registers.

Once we see the guest enabling both the MMU and the caches, we
can go back to a saner mode of operation, which is to leave these
registers in complete control of the guest.

Signed-off-by: Marc Zyngier 
Acked-by: Catalin Marinas 
Reviewed-by: Christoffer Dall 
Cc: Shannon Zhao 
Signed-off-by: Greg Kroah-Hartman

ARM: KVM: add world-switch for AMAIR{0,1}

2015-05-17T16:53:52+00:00

commit af20814ee927ed888288d98917a766b4179c4fe0 upstream.

HCR.TVM traps (among other things) accesses to AMAIR0 and AMAIR1.
In order to minimise the amount of surprise a guest could generate by
trying to access these registers with caches off, add them to the
list of registers we switch/handle.

Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Acked-by: Catalin Marinas 
Cc: Shannon Zhao 
Signed-off-by: Greg Kroah-Hartman

ARM: KVM: introduce per-vcpu HYP Configuration Register

2015-05-17T16:53:52+00:00

commit ac30a11e8e92a03dbe236b285c5cbae0bf563141 upstream.

So far, KVM/ARM used a fixed HCR configuration per guest, except for
the VI/VF/VA bits to control the interrupt in absence of VGIC.

With the upcoming need to dynamically reconfigure trapping, it becomes
necessary to allow the HCR to be changed on a per-vcpu basis.

The fix here is to mimic what KVM/arm64 already does: a per vcpu HCR
field, initialized at setup time.

Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Acked-by: Catalin Marinas 
Cc: Shannon Zhao 
Signed-off-by: Greg Kroah-Hartman

ARM: KVM: fix ordering of 64bit coprocessor accesses

2015-05-17T16:53:52+00:00

commit 547f781378a22b65c2ab468f235c23001b5924da upstream.

Commit 240e99cbd00a (ARM: KVM: Fix 64-bit coprocessor handling)
added an ordering dependency for the 64bit registers.

The order described is: CRn, CRm, Op1, Op2, 64bit-first.

Unfortunately, the implementation is: CRn, 64bit-first, CRm...

Move the 64bit test to be last in order to match the documentation.

Signed-off-by: Marc Zyngier 
Reviewed-by: Christoffer Dall 
Acked-by: Catalin Marinas 
Cc: Shannon Zhao 
Signed-off-by: Greg Kroah-Hartman