linux-stable.git/arch/xtensa/kernel, branch v3.8

xtensa: clean up files to make them code-style compliant

2012-12-19T05:10:25+00:00

Remove heading and trailing spaces, trim trailing lines, and wrap lines
that are longer than 80 characters.

Signed-off-by: Chris Zankel

xtensa: initialize CPENABLE SR when core has one

2012-12-19T05:10:25+00:00

XCHAL_CP_NUM is defined in variant/tie.h and it is not included by
head.S, leaving CPENABLE register uninitialised. XCHAL_HAVE_CP is
defined in variant/core.h to 1 when core has CPENABLE SR.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: reset all timers on initialization

2012-12-19T05:10:25+00:00

There are XCHAL_NUM_TIMERS, reset them all.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: add device trees support

2012-12-19T05:10:23+00:00

Device trees allow specification of hardware topology and device
parameters at runtime instead of hard-coding them in platform setup
code. This allows running single binary kernel on a range of compatible
boards.

New boot parameters tag BP_TAG_FDT is allocated and a pointer to flat
device tree is passed in it.

Note that current interrupt mapping scheme uses single cell for
interrupt identification. That means that IRQ numbers used in DTS must
be CPU internal IRQ numbers, not external. It is possible to extend
interrupt identification to two cells, and use second cell to tell
external IRQ numbers form internal. That would allow to use single DTS
on multiple boards with different mapping of external IRQ numbers.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: add IRQ domains support

2012-12-19T05:10:23+00:00

IRQ domains provide a mechanism for conversion of linux IRQ numbers to
hardware IRQ numbers and vice versus. It is used by OpenFirmware for
linking device tree objects to their respective interrupt controllers.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: add s32c1i sanity check

2012-12-19T05:10:22+00:00

Add a brief sanity test of S32C1I functionality.  This instruction
is needed by the kernel and userland as part of the base ABI
(including GCC atomic builtins, certain threading packages, future
atomic support in the C++ standard, etc).  However, correct operation
of this instruction requires some cooperation by hardware external to
the processor (such as bus bridge, bus fabric, or memory controller).
Minimally exercising this mechanism and reporting explicit status
early in the boot process is helpful to chip vendors using the Linux
kernel as a benchmark of correctness of hardware.

As it turns out, S32C1I is not exercised by the kernel and by uClibc
based userland as of early June 2008.  This is expected to change
soon as both incorporate more recent open source developments.

Signed-off-by: Marc Gauthier 
Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: add trap_set_handler function

2012-12-19T05:10:22+00:00

trap_set_handler sets new C-handler in the exception table and returns
previous handler.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: initialize atomctl SR

2012-12-19T05:10:22+00:00

In order to use S32C1I instruction on cores with ATOMCTL SR the register
must be properly initialized.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: save and restore scompare1 SR on kernel entry

2012-12-19T05:10:22+00:00

Although scompare1 may be saved/restored by xchal_ncp_{load,store}
macros, explicit save/restore of registers manipulated by the kernel
itself is considered more correct.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: display s32c1i feature flag in cpuinfo

2012-12-19T05:10:21+00:00

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel