linux-stable.git/arch/x86/kernel/amd_nb.c, branch linux-5.2.y

x86/amd_nb: Add PCI device IDs for family 17h, model 70h

2019-10-05T11:13:52+00:00

[ Upstream commit af4e1c5eca95bed1192d8dc45c8ed63aea2209e8 ]

The AMD Ryzen gen 3 processors came with a different PCI IDs for the
function 3 & 4 which are used to access the SMN interface. The root
PCI address however remained at the same address as the model 30h.

Adding the F3/F4 PCI IDs respectively to the misc and link ids appear
to be sufficient for k10temp, so let's add them and follow up on the
patch if other functions need more tweaking.

Vicki Pfau sent an identical patch after I checked that no-one had
written this patch. I would have been happy about dropping my patch but
unlike for his patch series, I had already Cc:ed the x86 people and
they already reviewed the changes. Since Vicki has not answered to
any email after his initial series, let's assume she is on vacation
and let's avoid duplication of reviews from the maintainers and merge
my series. To acknowledge Vicki's anteriority, I added her S-o-b to
the patch.

v2, suggested by Guenter Roeck and Brian Woods:
 - rename from 71h to 70h

Signed-off-by: Vicki Pfau 
Signed-off-by: Marcel Bocu 
Tested-by: Marcel Bocu 
Acked-by: Thomas Gleixner 
Acked-by: Brian Woods 
Acked-by: Bjorn Helgaas 	# pci_ids.h

Cc: Thomas Gleixner 
Cc: Ingo Molnar 
Cc: Borislav Petkov 
Cc: "H. Peter Anvin" 
Cc: x86@kernel.org
Cc: "Woods, Brian" 
Cc: Clemens Ladisch 
Cc: Jean Delvare 
Cc: Guenter Roeck 
Cc: linux-hwmon@vger.kernel.org
Link: https://lore.kernel.org/r/20190722174510.2179-1-marcel.p.bocu@gmail.com
Signed-off-by: Guenter Roeck 
Signed-off-by: Sasha Levin

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 477

2019-06-19T15:09:51+00:00

Based on 1 normalized pattern(s):

  subject to gplv2

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 1 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Enrico Weigelt 
Reviewed-by: Allison Randal 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081204.018005938@linutronix.de
Signed-off-by: Greg Kroah-Hartman

x86/amd_nb: Add PCI device IDs for family 17h, model 30h

2018-11-07T20:36:09+00:00

Add the PCI device IDs for family 17h model 30h, since they are needed
for accessing various registers via the data fabric/SMN interface.

Signed-off-by: Brian Woods 
Signed-off-by: Borislav Petkov 
CC: Bjorn Helgaas 
CC: Clemens Ladisch 
CC: Guenter Roeck 
CC: "H. Peter Anvin" 
CC: Ingo Molnar 
CC: Jean Delvare 
CC: Jia Zhang 
CC: 
CC: 
CC: Pu Wen 
CC: Thomas Gleixner 
CC: x86-ml 
Link: http://lkml.kernel.org/r/20181106200754.60722-4-brian.woods@amd.com

x86/amd_nb: Add support for newer PCI topologies

2018-11-07T20:28:29+00:00

Add support for new processors which have multiple PCI root complexes
per data fabric/system management network interface.  If there are (N)
multiple PCI roots per DF/SMN interface, then the PCI roots are
redundant (as far as SMN/DF access goes).  For each DF/SMN interface:
map to the first available PCI root and skip the next N-1 PCI roots so
the following DF/SMN interface get mapped to a correct PCI root.

Ex:
DF/SMN 0 -> 60
	    40
	    20
	    00
DF/SMN 1 -> e0
	    c0
	    a0
	    80

Signed-off-by: Brian Woods 
Signed-off-by: Borislav Petkov 
CC: Bjorn Helgaas 
CC: Clemens Ladisch 
CC: Guenter Roeck 
CC: "H. Peter Anvin" 
CC: Ingo Molnar 
CC: Jean Delvare 
CC: Jia Zhang 
CC: 
CC: 
CC: Pu Wen 
CC: Thomas Gleixner 
CC: x86-ml 
Link: http://lkml.kernel.org/r/20181106200754.60722-3-brian.woods@amd.com

hwmon/k10temp, x86/amd_nb: Consolidate shared device IDs

2018-11-07T20:28:04+00:00

Consolidate shared PCI_DEVICE_IDs that were scattered through k10temp
and amd_nb, and move them into pci_ids.

Signed-off-by: Brian Woods 
Signed-off-by: Borislav Petkov 
Acked-by: Guenter Roeck 
CC: Bjorn Helgaas 
CC: Clemens Ladisch 
CC: "H. Peter Anvin" 
CC: Ingo Molnar 
CC: Jean Delvare 
CC: Jia Zhang 
CC: 
CC: 
CC: Pu Wen 
CC: Thomas Gleixner 
CC: x86-ml 
Link: http://lkml.kernel.org/r/20181106200754.60722-2-brian.woods@amd.com

x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge

2018-09-27T16:28:58+00:00

Hygon's PCI vendor ID is 0x1d94, and there are PCI devices
0x1450/0x1463/0x1464 for the host bridge on the Hygon Dhyana platform.
Add Hygon Dhyana support to the PCI and northbridge subsystems by using
the code path of AMD family 17h.

 [ bp: Massage commit message, sort local vars into reverse xmas tree
   order and move the amd_northbridges.num check up. ]

Signed-off-by: Pu Wen 
Signed-off-by: Borislav Petkov 
Acked-by: Bjorn Helgaas 	# pci_ids.h
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Cc: helgaas@kernel.org
Cc: linux-pci@vger.kernel.org
Link: https://lkml.kernel.org/r/5f8877bd413f2ea0833378dd5454df0720e1c0df.1537885177.git.puwen@hygon.cn

x86/amd_nb: Check vendor in AMD-only functions

2018-09-27T16:28:58+00:00

Exit early in functions which are meant to run on AMD only but which get
run on different vendor (VMs, etc).

 [ bp: rewrite commit message. ]

Signed-off-by: Pu Wen 
Signed-off-by: Borislav Petkov 
Cc: bhelgaas@google.com
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Cc: helgaas@kernel.org
Link: https://lkml.kernel.org/r/487d8078708baedaf63eb00a82251e228b58f1c2.1537885177.git.puwen@hygon.cn

x86/amd_nb: Add support for Raven Ridge CPUs

2018-05-13T16:00:27+00:00

Add Raven Ridge root bridge and data fabric PCI IDs.
This is required for amd_pci_dev_to_node_id() and amd_smn_read().

Cc: stable@vger.kernel.org # v4.16+
Tested-by: Gabriel Craciunescu 
Acked-by: Thomas Gleixner 
Signed-off-by: Guenter Roeck

x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping

2018-02-15T00:15:52+00:00

x86_mask is a confusing name which is hard to associate with the
processor's stepping.

Additionally, correct an indent issue in lib/cpu.c.

Signed-off-by: Jia Zhang 
[ Updated it to more recent kernels. ]
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: bp@alien8.de
Cc: tony.luck@intel.com
Link: http://lkml.kernel.org/r/1514771530-70829-1-git-send-email-qianyue.zj@alibaba-inc.com
Signed-off-by: Ingo Molnar

x86/cpu/AMD: Apply the Erratum 688 fix when the BIOS doesn't

2017-10-22T11:06:02+00:00

Some F14h machines have an erratum which, "under a highly specific
and detailed set of internal timing conditions" can lead to skipping
instructions and RIP corruption.

Add the fix for those machines when their BIOS doesn't apply it or
there simply isn't BIOS update for them.

Tested-by: 
Signed-off-by: Borislav Petkov 
Cc: 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Sherry Hurwitz 
Cc: Thomas Gleixner 
Cc: Yazen Ghannam 
Link: http://lkml.kernel.org/r/20171022104731.28249-1-bp@alien8.de
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197285
[ Added pr_info() that we activated the workaround. ]
Signed-off-by: Ingo Molnar