linux-stable.git/arch/sh/kernel/setup.c, branch linux-2.6.31.y

sh: rework mode pin code

2009-06-11T06:08:53+00:00

This patch reworks the mode pin code to keep the pin
definitions in one place. The mode pins values are now
the value of the bit instead of bit number.

With this patch in place the sh7785 header file contains
mode pin comments. The sh7785 clock code and the sh7785lcr
board code are updated to reflect the new shared mode pins.

Signed-off-by: Magnus Damm 
Signed-off-by: Paul Mundt

sh: boot word / mode pin support V2

2009-06-01T06:44:49+00:00

Add mode pin support for the SuperH architecture V2.

With this patch applied the board code can add their
own function to export the cpu mode pin configuration.
In most cases this will be a constant bitmap, but
boards that allow reading this from a register can
instead read out the pin state from hardware.

The code warns if a pin is tested but no board specific
mode pin function has been provided.

Signed-off-by: Magnus Damm 
Signed-off-by: Paul Mundt

sh: Kill off the GENERIC_CALIBRATE_DELAY ifndef.

2009-05-08T13:14:01+00:00

Now that everyone is using the clock framework directly and we
unconditionally provide our own calibrate_delay() function, having it
wrapped in an ifndef is no longer useful. So, kill it off.

Signed-off-by: Paul Mundt

Merge branches 'sh/earlytimer' and 'sh/shmobile-r2r-staging'

2009-04-19T04:08:33+00:00

sh: Add plat_early_device_setup()

2009-04-19T04:06:25+00:00

Add a plat_early_device_setup() function to allow
processor-specific code to register Early Platform Data.

Signed-off-by: Magnus Damm 
Signed-off-by: Paul Mundt

sh: Add support for SH7724 (SH-Mobile R2R) CPU subtype.

2009-04-16T05:40:56+00:00

This implements initial support for the SH-Mobile R2R CPU.
Based on Rev 0.11 of the initial SH7724 hardware manual.

Signed-off-by: Kuninori Morimoto 
Signed-off-by: Paul Mundt

sh: Fix up -Wformat-security whining.

2009-03-30T23:25:54+00:00

Triggers -Werror on gcc-4.3:

arch/sh/kernel/setup.c: In function 'early_parse_mem':
arch/sh/kernel/setup.c:111: error: format not a string literal and no format arguments
...

Signed-off-by: Paul Mundt

sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.

2009-03-17T08:49:49+00:00

This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).

The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.

While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.

With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.

Signed-off-by: Paul Mundt

sh: Add support for SH7786 CPU subtype.

2009-03-03T06:40:25+00:00

This adds preliminary support for the SH7786 CPU subtype.

While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.

More information on this particular CPU subtype is available at:

	http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/

Signed-off-by: Kuninori Morimoto 
Signed-off-by: Paul Mundt

sh: Only reserve memory under CONFIG_ZERO_PAGE_OFFSET when it != 0.

2009-01-29T02:56:02+00:00

Signed-off-by: Chris Smith 
Signed-off-by: Stuart Menefy 
Signed-off-by: Paul Mundt