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<title>linux-stable.git/arch/riscv, branch linux-5.0.y</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>riscv: fix accessing 8-byte variable from RV32</title>
<updated>2019-05-08T05:22:50+00:00</updated>
<author>
<name>Alan Kao</name>
<email>alankao@andestech.com</email>
</author>
<published>2019-03-22T06:37:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=603ae6024626ae227fcac0ec75b9a2f907827765'/>
<id>603ae6024626ae227fcac0ec75b9a2f907827765</id>
<content type='text'>
[ Upstream commit dbee9c9c45846f003ec2f819710c2f4835630a6a ]

A memory save operation to 8-byte variable in RV32 is divided into
two sw instructions in the put_user macro.  The current fixup returns
execution flow to the second sw instead of the one after it.

This patch fixes this fixup code according to the load access part.

Signed-off-by: Alan Kao&lt;alankao@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Cc: Vincent Chen &lt;deanbo422@gmail.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Signed-off-by: Sasha Levin (Microsoft) &lt;sashal@kernel.org&gt;
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<pre>
[ Upstream commit dbee9c9c45846f003ec2f819710c2f4835630a6a ]

A memory save operation to 8-byte variable in RV32 is divided into
two sw instructions in the put_user macro.  The current fixup returns
execution flow to the second sw instead of the one after it.

This patch fixes this fixup code according to the load access part.

Signed-off-by: Alan Kao&lt;alankao@andestech.com&gt;
Cc: Greentime Hu &lt;greentime@andestech.com&gt;
Cc: Vincent Chen &lt;deanbo422@gmail.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Signed-off-by: Sasha Levin (Microsoft) &lt;sashal@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: Fix syscall_get_arguments() and syscall_set_arguments()</title>
<updated>2019-04-17T06:39:50+00:00</updated>
<author>
<name>Dmitry V. Levin</name>
<email>ldv@altlinux.org</email>
</author>
<published>2019-03-29T17:12:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=6a184be78d3fd819361ba7a42d2e00d8ecdf9d3c'/>
<id>6a184be78d3fd819361ba7a42d2e00d8ecdf9d3c</id>
<content type='text'>
commit 10a16997db3d99fc02c026cf2c6e6c670acafab0 upstream.

RISC-V syscall arguments are located in orig_a0,a1..a5 fields
of struct pt_regs.

Due to an off-by-one bug and a bug in pointer arithmetic
syscall_get_arguments() was reading s3..s7 fields instead of a1..a5.
Likewise, syscall_set_arguments() was writing s3..s7 fields
instead of a1..a5.

Link: http://lkml.kernel.org/r/20190329171221.GA32456@altlinux.org

Fixes: e2c0cdfba7f69 ("RISC-V: User-facing API")
Cc: Ingo Molnar &lt;mingo@redhat.com&gt;
Cc: Kees Cook &lt;keescook@chromium.org&gt;
Cc: Andy Lutomirski &lt;luto@amacapital.net&gt;
Cc: Will Drewry &lt;wad@chromium.org&gt;
Cc: Albert Ou &lt;aou@eecs.berkeley.edu&gt;
Cc: linux-riscv@lists.infradead.org
Cc: stable@vger.kernel.org # v4.15+
Acked-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Signed-off-by: Dmitry V. Levin &lt;ldv@altlinux.org&gt;
Signed-off-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
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<pre>
commit 10a16997db3d99fc02c026cf2c6e6c670acafab0 upstream.

RISC-V syscall arguments are located in orig_a0,a1..a5 fields
of struct pt_regs.

Due to an off-by-one bug and a bug in pointer arithmetic
syscall_get_arguments() was reading s3..s7 fields instead of a1..a5.
Likewise, syscall_set_arguments() was writing s3..s7 fields
instead of a1..a5.

Link: http://lkml.kernel.org/r/20190329171221.GA32456@altlinux.org

Fixes: e2c0cdfba7f69 ("RISC-V: User-facing API")
Cc: Ingo Molnar &lt;mingo@redhat.com&gt;
Cc: Kees Cook &lt;keescook@chromium.org&gt;
Cc: Andy Lutomirski &lt;luto@amacapital.net&gt;
Cc: Will Drewry &lt;wad@chromium.org&gt;
Cc: Albert Ou &lt;aou@eecs.berkeley.edu&gt;
Cc: linux-riscv@lists.infradead.org
Cc: stable@vger.kernel.org # v4.15+
Acked-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Signed-off-by: Dmitry V. Levin &lt;ldv@altlinux.org&gt;
Signed-off-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "RISC-V: Make BSS section as the last section in vmlinux.lds.S"</title>
<updated>2019-02-11T23:24:45+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@sifive.com</email>
</author>
<published>2019-02-08T17:11:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=41fb9d54f12b87fb1f670653e95d34668a08e8ee'/>
<id>41fb9d54f12b87fb1f670653e95d34668a08e8ee</id>
<content type='text'>
At least BBL relies on the flat binaries containing all the bytes in the
actual image to exist in the file.  Before this revert the flat images
dropped the trailing zeros, which caused BBL to put its copy of the
device tree where Linux thought the BSS was, which wreaks all sorts of
havoc.  Manifesting the bug is a bit subtle because BBL aligns
everything to 2MiB page boundaries, but with large enough kernels you're
almost certain to get bitten by the bug.

While moving the sections around isn't a great long-term fix, it will at
least avoid producing broken images.

This reverts commit 22e6a2e14cb8ebcae059488cf24e778e4058c2bf.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
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<pre>
At least BBL relies on the flat binaries containing all the bytes in the
actual image to exist in the file.  Before this revert the flat images
dropped the trailing zeros, which caused BBL to put its copy of the
device tree where Linux thought the BSS was, which wreaks all sorts of
havoc.  Manifesting the bug is a bit subtle because BBL aligns
everything to 2MiB page boundaries, but with large enough kernels you're
almost certain to get bitten by the bug.

While moving the sections around isn't a great long-term fix, it will at
least avoid producing broken images.

This reverts commit 22e6a2e14cb8ebcae059488cf24e778e4058c2bf.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: Add pte bit to distinguish swap from invalid</title>
<updated>2019-02-11T23:24:45+00:00</updated>
<author>
<name>Stefan O'Rear</name>
<email>sorear2@gmail.com</email>
</author>
<published>2018-12-16T18:03:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=e3613bb8afc2a9474c9214d65c8326c5ac02135e'/>
<id>e3613bb8afc2a9474c9214d65c8326c5ac02135e</id>
<content type='text'>
Previously, invalid PTEs and swap PTEs had the same binary
representation, causing errors when attempting to unmap PROT_NONE
mappings, including implicit unmap on exit.

Typical error:

swap_info_get: Bad swap file entry 40000000007a9879
BUG: Bad page map in process a.out  pte:3d4c3cc0 pmd:3e521401

Cc: stable@vger.kernel.org
Signed-off-by: Stefan O'Rear &lt;sorear2@gmail.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Previously, invalid PTEs and swap PTEs had the same binary
representation, causing errors when attempting to unmap PROT_NONE
mappings, including implicit unmap on exit.

Typical error:

swap_info_get: Bad swap file entry 40000000007a9879
BUG: Bad page map in process a.out  pte:3d4c3cc0 pmd:3e521401

Cc: stable@vger.kernel.org
Signed-off-by: Stefan O'Rear &lt;sorear2@gmail.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: Adjust mmap base address at a third of task size</title>
<updated>2019-01-25T18:50:53+00:00</updated>
<author>
<name>Alexandre Ghiti</name>
<email>aghiti@upmem.com</email>
</author>
<published>2018-12-10T06:21:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=ae662eec8a515ab550524e04c793b5ddf1aae3a1'/>
<id>ae662eec8a515ab550524e04c793b5ddf1aae3a1</id>
<content type='text'>
This ratio is the most used among all other architectures and make
icache_hygiene libhugetlbfs test pass: this test mmap lots of
hugepages whose addresses, without this patch, reach the end of
the process user address space.

Signed-off-by: Alexandre Ghiti &lt;aghiti@upmem.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This ratio is the most used among all other architectures and make
icache_hygiene libhugetlbfs test pass: this test mmap lots of
hugepages whose addresses, without this patch, reach the end of
the process user address space.

Signed-off-by: Alexandre Ghiti &lt;aghiti@upmem.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: fixup max_low_pfn with PFN_DOWN.</title>
<updated>2019-01-24T01:51:53+00:00</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2019-01-12T08:16:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=28198c4639b39899a728ac89aea29d2a7a72562f'/>
<id>28198c4639b39899a728ac89aea29d2a7a72562f</id>
<content type='text'>
max_low_pfn should be pfn_size not byte_size.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Signed-off-by: Mao Han &lt;mao_han@c-sky.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
max_low_pfn should be pfn_size not byte_size.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Signed-off-by: Mao Han &lt;mao_han@c-sky.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: defconfig: Add CRYPTO_DEV_VIRTIO=y</title>
<updated>2019-01-23T22:09:01+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@sifive.com</email>
</author>
<published>2019-01-23T22:09:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=2a200fb9fb124e2889516c4668c5483bf7107044'/>
<id>2a200fb9fb124e2889516c4668c5483bf7107044</id>
<content type='text'>
This allows acceleration of cryptography inside QEMU.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This allows acceleration of cryptography inside QEMU.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: defconfig: Enable Generic PCIE by default</title>
<updated>2019-01-23T22:07:46+00:00</updated>
<author>
<name>Alistair Francis</name>
<email>Alistair.Francis@wdc.com</email>
</author>
<published>2019-01-12T00:41:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=e4cf9e47ab244977d12513bb4610a44f88ad5e68'/>
<id>e4cf9e47ab244977d12513bb4610a44f88ad5e68</id>
<content type='text'>
Enable generic PCIe by default in the RISC-V defconfig, this allows us
to use QEMU's PCIe support out of the box.  CONFIG_RAS=y is
automatically selected by generic PCIe, so it has been dropped from
the defconfig.

Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
[Palmer: Split out PCIE_XILINX and CRYPTO_DEV_VIRTIO]
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enable generic PCIe by default in the RISC-V defconfig, this allows us
to use QEMU's PCIe support out of the box.  CONFIG_RAS=y is
automatically selected by generic PCIe, so it has been dropped from
the defconfig.

Signed-off-by: Alistair Francis &lt;alistair.francis@wdc.com&gt;
[Palmer: Split out PCIE_XILINX and CRYPTO_DEV_VIRTIO]
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: defconfig: Move CONFIG_PCI{,E_XILINX}</title>
<updated>2019-01-23T20:59:17+00:00</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@sifive.com</email>
</author>
<published>2019-01-23T20:59:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=a37ead8f2efb1595c15079eddac2672630f750ea'/>
<id>a37ead8f2efb1595c15079eddac2672630f750ea</id>
<content type='text'>
eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
reorganized the PCI-related Kconfig entries and resulted in a diff in
our defconfig.  This simply removes the diff.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
reorganized the PCI-related Kconfig entries and resulted in a diff in
our defconfig.  This simply removes the diff.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: Kconfig: fix spelling mistake "traget" -&gt; "target"</title>
<updated>2019-01-23T20:56:20+00:00</updated>
<author>
<name>Antony Pavlov</name>
<email>antonynpavlov@gmail.com</email>
</author>
<published>2019-01-08T19:45:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=86cca81a31cdc6f1f292b5b0c6a4e7e06863cdc9'/>
<id>86cca81a31cdc6f1f292b5b0c6a4e7e06863cdc9</id>
<content type='text'>
Signed-off-by: Antony Pavlov &lt;antonynpavlov@gmail.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Antony Pavlov &lt;antonynpavlov@gmail.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</pre>
</div>
</content>
</entry>
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