<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/arch/riscv/kvm/vcpu_vector.c, branch linux-rolling-stable</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>riscv: kvm: fix vector context allocation leak</title>
<updated>2026-05-14T13:31:14+00:00</updated>
<author>
<name>Osama Abdelkader</name>
<email>osama.abdelkader@gmail.com</email>
</author>
<published>2026-03-16T15:16:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=1d57ab45ec5c0e22789de793bcf2a31ad6fb7d98'/>
<id>1d57ab45ec5c0e22789de793bcf2a31ad6fb7d98</id>
<content type='text'>
commit b7c958d7c1eb1cb9b2be7b5ee4129fcd66cec978 upstream.

When the second kzalloc (host_context.vector.datap) fails in
kvm_riscv_vcpu_alloc_vector_context, the first allocation
(guest_context.vector.datap) is leaked. Free it before returning.

Fixes: 0f4b82579716 ("riscv: KVM: Add vector lazy save/restore support")
Cc: stable@vger.kernel.org
Signed-off-by: Osama Abdelkader &lt;osama.abdelkader@gmail.com&gt;
Reviewed-by: Andy Chiu &lt;andybnac@gmail.com&gt;
Link: https://lore.kernel.org/r/20260316151612.13305-1-osama.abdelkader@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit b7c958d7c1eb1cb9b2be7b5ee4129fcd66cec978 upstream.

When the second kzalloc (host_context.vector.datap) fails in
kvm_riscv_vcpu_alloc_vector_context, the first allocation
(guest_context.vector.datap) is leaked. Free it before returning.

Fixes: 0f4b82579716 ("riscv: KVM: Add vector lazy save/restore support")
Cc: stable@vger.kernel.org
Signed-off-by: Osama Abdelkader &lt;osama.abdelkader@gmail.com&gt;
Reviewed-by: Andy Chiu &lt;andybnac@gmail.com&gt;
Link: https://lore.kernel.org/r/20260316151612.13305-1-osama.abdelkader@gmail.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: KVM: fix stack overrun when loading vlenb</title>
<updated>2025-08-25T04:56:20+00:00</updated>
<author>
<name>Radim Krčmář</name>
<email>rkrcmar@ventanamicro.com</email>
</author>
<published>2025-08-05T10:44:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=799766208f09f95677a9ab111b93872d414fbad7'/>
<id>799766208f09f95677a9ab111b93872d414fbad7</id>
<content type='text'>
The userspace load can put up to 2048 bits into an xlen bit stack
buffer.  We want only xlen bits, so check the size beforehand.

Fixes: 2fa290372dfe ("RISC-V: KVM: add 'vlenb' Vector CSR")
Cc: stable@vger.kernel.org
Signed-off-by: Radim Krčmář &lt;rkrcmar@ventanamicro.com&gt;
Reviewed-by: Nutty Liu &lt;liujingqi@lanxincomputing.com&gt;
Reviewed-by: Daniel Henrique Barboza &lt;dbarboza@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20250805104418.196023-4-rkrcmar@ventanamicro.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The userspace load can put up to 2048 bits into an xlen bit stack
buffer.  We want only xlen bits, so check the size beforehand.

Fixes: 2fa290372dfe ("RISC-V: KVM: add 'vlenb' Vector CSR")
Cc: stable@vger.kernel.org
Signed-off-by: Radim Krčmář &lt;rkrcmar@ventanamicro.com&gt;
Reviewed-by: Nutty Liu &lt;liujingqi@lanxincomputing.com&gt;
Reviewed-by: Daniel Henrique Barboza &lt;dbarboza@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20250805104418.196023-4-rkrcmar@ventanamicro.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>KVM: RISC-V: refactor vector state reset</title>
<updated>2025-05-21T04:04:46+00:00</updated>
<author>
<name>Radim Krčmář</name>
<email>rkrcmar@ventanamicro.com</email>
</author>
<published>2025-04-03T11:25:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=9ffecf04144db5517eae204e65b7cde75ac920e0'/>
<id>9ffecf04144db5517eae204e65b7cde75ac920e0</id>
<content type='text'>
Do not depend on the reset structures.

vector.datap is a kernel memory pointer that needs to be preserved as it
is not a part of the guest vector data.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Radim Krčmář &lt;rkrcmar@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20250403112522.1566629-4-rkrcmar@ventanamicro.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Do not depend on the reset structures.

vector.datap is a kernel memory pointer that needs to be preserved as it
is not a part of the guest vector data.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Radim Krčmář &lt;rkrcmar@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20250403112522.1566629-4-rkrcmar@ventanamicro.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: KVM: add 'vlenb' Vector CSR</title>
<updated>2023-12-29T07:01:54+00:00</updated>
<author>
<name>Daniel Henrique Barboza</name>
<email>dbarboza@ventanamicro.com</email>
</author>
<published>2023-12-05T17:45:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=2fa290372dfe7dd248b1c16f943f273a3e674f22'/>
<id>2fa290372dfe7dd248b1c16f943f273a3e674f22</id>
<content type='text'>
Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise
it is not possible to retrieve any vector reg since we're returning
EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()).

Signed-off-by: Daniel Henrique Barboza &lt;dbarboza@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise
it is not possible to retrieve any vector reg since we're returning
EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()).

Signed-off-by: Daniel Henrique Barboza &lt;dbarboza@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context()</title>
<updated>2023-12-29T07:01:53+00:00</updated>
<author>
<name>Daniel Henrique Barboza</name>
<email>dbarboza@ventanamicro.com</email>
</author>
<published>2023-12-05T17:45:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=197bd237b67268651ac544e8fedbe1fd275d41e0'/>
<id>197bd237b67268651ac544e8fedbe1fd275d41e0</id>
<content type='text'>
'vlenb', added to riscv_v_ext_state by commit c35f3aa34509 ("RISC-V:
vector: export VLENB csr in __sc_riscv_v_state"), isn't being
initialized in guest_context. If we export 'vlenb' as a KVM CSR,
something we want to do in the next patch, it'll always return 0.

Set 'vlenb' to riscv_v_size/32.

Signed-off-by: Daniel Henrique Barboza &lt;dbarboza@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
'vlenb', added to riscv_v_ext_state by commit c35f3aa34509 ("RISC-V:
vector: export VLENB csr in __sc_riscv_v_state"), isn't being
initialized in guest_context. If we export 'vlenb' as a KVM CSR,
something we want to do in the next patch, it'll always return 0.

Set 'vlenb' to riscv_v_size/32.

Signed-off-by: Daniel Henrique Barboza &lt;dbarboza@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: Rearrange hwcap.h and cpufeature.h</title>
<updated>2023-11-09T18:15:51+00:00</updated>
<author>
<name>Xiao Wang</name>
<email>xiao.w.wang@intel.com</email>
</author>
<published>2023-10-31T06:45:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=e72c4333d2f2e7f2200f71a88c0480fd2a769a64'/>
<id>e72c4333d2f2e7f2200f71a88c0480fd2a769a64</id>
<content type='text'>
Now hwcap.h and cpufeature.h are mutually including each other, and most of
the variable/API declarations in hwcap.h are implemented in cpufeature.c,
so, it's better to move them into cpufeature.h and leave only macros for
ISA extension logical IDs in hwcap.h.

BTW, the riscv_isa_extension_mask macro is not used now, so this patch
removes it.

Suggested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Xiao Wang &lt;xiao.w.wang@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20231031064553.2319688-2-xiao.w.wang@intel.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Now hwcap.h and cpufeature.h are mutually including each other, and most of
the variable/API declarations in hwcap.h are implemented in cpufeature.c,
so, it's better to move them into cpufeature.h and leave only macros for
ISA extension logical IDs in hwcap.h.

BTW, the riscv_isa_extension_mask macro is not used now, so this patch
removes it.

Suggested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Xiao Wang &lt;xiao.w.wang@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Link: https://lore.kernel.org/r/20231031064553.2319688-2-xiao.w.wang@intel.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: KVM: Improve vector save/restore functions</title>
<updated>2023-08-08T11:56:05+00:00</updated>
<author>
<name>Andrew Jones</name>
<email>ajones@ventanamicro.com</email>
</author>
<published>2023-08-04T13:56:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=630b4cee9c378e2dbb56ed84f71fc2fac50b716e'/>
<id>630b4cee9c378e2dbb56ed84f71fc2fac50b716e</id>
<content type='text'>
Make two nonfunctional changes to the vector get/set vector reg
functions and their supporting function for simplification and
readability. The first is to not pass KVM_REG_RISCV_VECTOR, but
rather integrate it directly into the masking. The second is to
rename reg_val to reg_addr where and address is used instead of
a value.

Also opportunistically touch up some of the code formatting for
a third nonfunctional change.

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Daniel Henrique Barboza &lt;dbarboza@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make two nonfunctional changes to the vector get/set vector reg
functions and their supporting function for simplification and
readability. The first is to not pass KVM_REG_RISCV_VECTOR, but
rather integrate it directly into the masking. The second is to
rename reg_val to reg_addr where and address is used instead of
a value.

Also opportunistically touch up some of the code formatting for
a third nonfunctional change.

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Daniel Henrique Barboza &lt;dbarboza@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>RISC-V: KVM: Improve vector save/restore errors</title>
<updated>2023-08-08T11:56:00+00:00</updated>
<author>
<name>Andrew Jones</name>
<email>ajones@ventanamicro.com</email>
</author>
<published>2023-08-03T16:33:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=1deaf754f5310e348e6386e75b7f16a0089fa3b7'/>
<id>1deaf754f5310e348e6386e75b7f16a0089fa3b7</id>
<content type='text'>
kvm_riscv_vcpu_(get/set)_reg_vector() now returns ENOENT if V is not
available, EINVAL if reg type is not of VECTOR type, and any error that
might be thrown by kvm_riscv_vcpu_vreg_addr().

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
kvm_riscv_vcpu_(get/set)_reg_vector() now returns ENOENT if V is not
available, EINVAL if reg type is not of VECTOR type, and any error that
might be thrown by kvm_riscv_vcpu_vreg_addr().

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: KVM: Add vector lazy save/restore support</title>
<updated>2023-06-08T14:16:51+00:00</updated>
<author>
<name>Vincent Chen</name>
<email>vincent.chen@sifive.com</email>
</author>
<published>2023-06-05T11:07:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=0f4b82579716b12bb88257bd7ea80f25c791fb2c'/>
<id>0f4b82579716b12bb88257bd7ea80f25c791fb2c</id>
<content type='text'>
This patch adds vector context save/restore for guest VCPUs. To reduce the
impact on KVM performance, the implementation imitates the FP context
switch mechanism to lazily store and restore the vector context only when
the kernel enters/exits the in-kernel run loop and not during the KVM
world switch.

Signed-off-by: Vincent Chen &lt;vincent.chen@sifive.com&gt;
Signed-off-by: Greentime Hu &lt;greentime.hu@sifive.com&gt;
Signed-off-by: Andy Chiu &lt;andy.chiu@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Acked-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20230605110724.21391-20-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds vector context save/restore for guest VCPUs. To reduce the
impact on KVM performance, the implementation imitates the FP context
switch mechanism to lazily store and restore the vector context only when
the kernel enters/exits the in-kernel run loop and not during the KVM
world switch.

Signed-off-by: Vincent Chen &lt;vincent.chen@sifive.com&gt;
Signed-off-by: Greentime Hu &lt;greentime.hu@sifive.com&gt;
Signed-off-by: Andy Chiu &lt;andy.chiu@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Acked-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20230605110724.21391-20-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
