linux-stable.git/arch/riscv/kernel/head.S, branch linux-5.2.y Linux kernel stable tree treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 2019-06-05T15:36:37+00:00 Thomas Gleixner tglx@linutronix.de 2019-05-29T14:18:00+00:00 50acfb2b76e19f73270fef9a32726c7e18d08ec3 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation version 2 this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 97 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141901.025053186@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation version 2 this program is distributed
  in the hope that it will be useful but without any warranty without
  even the implied warranty of merchantability or fitness for a
  particular purpose see the gnu general public license for more
  details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 97 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141901.025053186@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
RISC-V: Avoid using invalid intermediate translations 2019-05-17T03:42:13+00:00 Palmer Dabbelt palmer@sifive.com 2019-03-27T00:40:24+00:00 4c3aeb82a0f4612bf0d94fbf74c3738db2c32fe5 This is almost entirely a comment. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> 
This is almost entirely a comment.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
RISC-V: Access CSRs using CSR numbers 2019-05-17T03:42:11+00:00 Anup Patel Anup.Patel@wdc.com 2019-04-25T08:38:41+00:00 a3182c91ef4e7dda90ff080a4132efd3ecb8786a We should prefer accessing CSRs using their CSR numbers because: 1. It compiles fine with older toolchains. 2. We can use latest CSR names in #define macro names of CSR numbers as-per RISC-V spec. 3. We can access newly added CSRs even if toolchain does not recognize newly addes CSRs by name. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
We should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
   as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not recognize
   newly addes CSRs by name.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
riscv: cleanup the parse_dtb calling conventions 2019-04-25T21:51:11+00:00 Christoph Hellwig hch@lst.de 2019-04-15T09:14:38+00:00 ba9c0141941ce618b04361a772c92a4da6dfcb35 No need to pass the hartid, and the dtb address passed is a physical address, so don't pretend it is a kernel pointer. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
No need to pass the hartid, and the dtb address passed is a physical
address, so don't pretend it is a kernel pointer.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
riscv: simplify the stack pointer setup in head.S 2019-04-25T21:51:10+00:00 Christoph Hellwig hch@lst.de 2019-04-15T09:14:37+00:00 c637b911e0669753ba85f8d61f10ca4b8f441dd3 We don't need THREAD_SIZE in asm-offsets.c as we can just calculate the value of init_thread_union + THREAD_SIZE using cpp, just like we do a few lines above. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
We don't need THREAD_SIZE in asm-offsets.c as we can just calculate
the value of init_thread_union + THREAD_SIZE using cpp, just like
we do a few lines above.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
riscv: clear all pending interrupts when booting 2019-04-25T21:51:10+00:00 Christoph Hellwig hch@lst.de 2019-04-15T09:14:36+00:00 df16c40cbfb43fbd6d5d879585b268b131fa95eb Just in case an old interrupt is pending make sure we clear everything asserted before this kernel started. Based on similar M-mode code in opensbi. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Nick Kossifidis <mick@ics.forth.gr> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
Just in case an old interrupt is pending make sure we clear everything
asserted before this kernel started.  Based on similar M-mode code in
opensbi.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Nick Kossifidis <mick@ics.forth.gr>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: Build flat and compressed kernel images 2018-11-20T13:19:09+00:00 Anup Patel anup@brainfault.org 2018-11-12T05:55:15+00:00 c0fbcd9918607e85c9598bfa3dd0a84ed77ea210 This patch extends Linux RISC-V build system to build and install: Image - Flat uncompressed kernel image Image.gz - Flat and GZip compressed kernel image Quiet a few bootloaders (such as Uboot, UEFI, etc) are capable of booting flat and compressed kernel images. In case of Uboot, booting Image or Image.gz is achieved using bootm command. The flat and uncompressed kernel image (i.e. Image) is very useful in pre-silicon developent and testing because we can create back-door HEX files for RAM on FPGAs from Image. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
This patch extends Linux RISC-V build system to build and install:
Image - Flat uncompressed kernel image
Image.gz - Flat and GZip compressed kernel image

Quiet a few bootloaders (such as Uboot, UEFI, etc) are capable of
booting flat and compressed kernel images. In case of Uboot, booting
Image or Image.gz is achieved using bootm command.

The flat and uncompressed kernel image (i.e. Image) is very useful
in pre-silicon developent and testing because we can create back-door
HEX files for RAM on FPGAs from Image.

Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: Use Linux logical CPU number instead of hartid 2018-10-23T00:03:37+00:00 Atish Patra atish.patra@wdc.com 2018-10-02T19:15:05+00:00 f99fb607fb2bc0d4ce6b9adb764c65e37f40a92b Setup the cpu_logical_map during boot. Moreover, every SBI call and PLIC context are based on the physical hartid. Use the logical CPU to hartid mapping to pass correct hartid to respective functions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
Setup the cpu_logical_map during boot. Moreover, every SBI call
and PLIC context are based on the physical hartid. Use the logical
CPU to hartid mapping to pass correct hartid to respective functions.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
RISC-V: Add the directive for alignment of stvec's value 2018-08-13T15:31:31+00:00 Zong Li zong@andestech.com 2018-08-02T15:21:56+00:00 94f592f0e5b9c17a7505119a2d6c0f1f529ae93d The stvec's value must be 4 byte alignment by specification definition. These directives avoid to stvec be set the non-alignment value. Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Rename sbi_save to parse_dtb to improve code readability 2018-02-20T18:56:26+00:00 Michael Clark michaeljclark@mac.com 2018-02-15T20:30:29+00:00 8b08f50152ff85a4780e5c385d2b65889406e842 The sbi_ prefix would seem to indicate an SBI interface, and save is not very specific. After applying this patch, reading head.S makes more sense. Signed-off-by: Michael Clark <michaeljclark@mac.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> 
The sbi_ prefix would seem to indicate an SBI interface, and save is not
very specific. After applying this patch, reading head.S makes more sense.

Signed-off-by: Michael Clark <michaeljclark@mac.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>