Pull SoC devicetree updates from Arnd Bergmann:
 "There are fewer devicetree updates this time that the last few ones,
  with five SoC types getting added:

   - Qualcomm Dragonwing IPQ9650 is a new wireless networking SoC using
     four Cortex-A55 and one Cortex-A78 core, which is a significant
     upgrade from older generations

   - ZTE zx297520v3 is an older low-end wireless SoC using a single
     Cortex-A53 core, which so far can only run 32-bit kernels. This
     brings back the ZX family of chips that was removed in 2021 after
     support for the original zx296702 and zx296718 chips was never
     completed.

   - Renesas R-Car M3Le (R8A779MD) is a variant of the R-Car M3-N
     (R8A77965) automotive SoC.

   - Apple t8122 (M3) is the 2023 generation of their laptop SoCs, which
     has now been reverse-engineered to the point of having initial
     kernel support for five laptop models.

   - ASPEED AST27xx is their first baseboard managment controller using
     a 64-bit core, the Cortex-A35, following earlier generations using
     ARMv5/v6/v7 CPUs.

  These all come with one or more initial boards, and in total there are
  39 new boards getting added across SoC families, including:

   - Two NAS boxes using the old Cortina Systems Gemini SoC based on an
     ARMv4 FA526 CPU core

   - 18 industrial embedded boards using NXP i.MX6/8/9 and LX2160A SoCs
     from Variscite, Toradex and SolidRun, plus a number of overlays for
     combinations with additional boards

   - One new carrier board and SoM using TI K3 AM62x, in addition to new
     overlays for older SoMs

   - Two new boards using Spacemit K3 (no relation with TI) RISC-V SoCs.

   - Three phones from Google, Nothing and Motorola, all using Qualcomm
     Snapdragon SoCs

   - AST26xx BMC support for two server boards

  While there is still a significant number of patches improving
  hardware support for the existing boards across vendors (NXP,
  Qualcomm, Renesas, Rockchips, Mediatek, ...), a much smaller number
  of cleanups and warning fixes have made it in this time"

* tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (665 commits)
  arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme
  arm64: dts: bst: enable eMMC controller in C1200
  dt-bindings: display/lvds-codec: add ti,sn65lvds93
  arm64: dts: allwinner: a523: Add missing GPIO interrupt
  arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap
  arm64: dts: aspeed: Add initial AST27xx SoC device tree
  arm64: Kconfig: Add ASPEED SoC family Kconfig support
  dt-bindings: arm: aspeed: Add AST2700 board compatible
  arm64: dts: allwinner: a523: add gpadc node
  arm64: dts: allwinner: Add EL2 virtual timer interrupt
  ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
  dt-bindings: media: sun6i-a31-isp: Add optional interconnect properties
  dt-bindings: media: sun6i-a31-csi: Add optional interconnect properties
  arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlays
  arm64: dts: imx93-var-som-symphony: enable ADC
  arm64: dts: imx93-var-som-symphony: enable TPM3 PWM
  arm64: dts: imx93-var-som-symphony: keep RGB_SEL low
  arm64: dts: imx93-var-som-symphony: enable UART7
  arm64: dts: imx93-var-som-symphony: add TPM support
  arm64: dts: imx91-var-som-symphony: fix RGB_SEL handling
  ...

Allwinner device tree changes for 7.2 - Take 2

Some changes for old chips and some for recent ones.

- A83T gained the MIPI CSI-2 receiver
- overlays enabled for Pine64 boards
- D1s / T113 and H616 gained the high speed timer
- T113s watchdog enabled (for reboot)
- H616 gained proper SRAM regions
- A523 family gained EL2 virtual timer interrupt and GPADC
- A523 pinctrl IRQ fix

* tag 'sunxi-dt-for-7.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: a523: Add missing GPIO interrupt
  arm64: dts: allwinner: a523: add gpadc node
  arm64: dts: allwinner: Add EL2 virtual timer interrupt
  ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
  dt-bindings: media: sun6i-a31-isp: Add optional interconnect properties
  dt-bindings: media: sun6i-a31-csi: Add optional interconnect properties
  arm64: dts: allwinner: sun50i-a64: Enable DT overlays
  arm: dts: allwinner: t113s: enable watchdog for reboot
  arm64: dts: allwinner: h616: add hstimer node
  riscv: dts: allwinner: d1s-t113: add hstimer node
  arm64: dts: allwinner: sun50i-h616: Add SRAM nodes

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Microchip RISC-V devicetrees for v7.2

This time around, there's nothing other than patches for Microchip
boards. All of this is low priority fixes and cleanup, centred on the
pic64gx and beaglev-fire boards. There is no new support added.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: microchip: remove redudant enabling of syscontroller
  riscv: dts: microchip: fix pic64gx gpio interrupt-cells
  riscv: dts: microchip: add gpio line names on beaglev-fire
  riscv: dts: microchip: add adc interrupt on beaglev-fire
  riscv: dts: microchip: clean up beaglev-fire regulator node names
  riscv: dts: microchip: remove gpio hogs from beaglev-fire
  riscv: dts: microchip: gpio controllers on mpfs need 2 interrupt cells
  riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically
  riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC
  riscv: dts: microchip: add tsu clock to macb on pic64gx

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

RISC-V Devicetrees for v7.2

Sophgo:

For CV18xx serials:
- Add bindings for Milk-V "Duo S" board.

For SG2042:
- The CPU unit address incorrectly used decimal numbers,
  especially for those nodes which value >= 10. Now
  corrected to use hexadecimal.
- The MSI controller actually only supports 16 interrupts;
  corrected to match the actual situation.
- PCIe RCs are cache-coherent with the CPU. Marked it out
  for RC nodes.

For SG2044:
- The same as SG2042, use hex for CPU unit address.

In additional, update Chen Wang's email address for Sopgho
SoC maintainer.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* tag 'riscv-sophgo-dt-for-v7.2' of https://github.com/sophgo/linux:
  riscv: dts: sophgo: reduce SG2042 MSI count to 16
  riscv: dts: sophgo: sg2042: use hex for CPU unit address
  riscv: dts: sophgo: sg2044: use hex for CPU unit address
  riscv: dts: sophgo: Add dma-coherent to SG2042 PCIe controllers
  dt-bindings: soc: sophgo: add sg2000 plic and clint documentation
  dt-bindings: soc: sophgo: add Milk-V Duo S board compatibles
  MAINTAINERS: update Chen Wang's email address

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

RISC-V SpacemiT DT changes for 7.2

For K3 SoC
- Add Ziccrse extension
- Add PWM support
- Add PDMA support
- Add USB2.0 support
- Add CoM260-IFX board
- Add DeepComputing FML13V05 board
- Fix I/O power of pinctrl

For K1 SoC
- Add Micro SD card support
- Add baudrate to console
- Add SPI support
- Enable thermal sensor
- Fix 32K clock

For boards of K1
- Milk-V Jupiter
  - Enable eMMC
- MusePi-Pro
  - Enable EEPROM/PCIe/QSPI/USB
- OrangePi R2S
  - Enable PMIC/USB3
- OrangePi RV2
  - Enable eMMC/I2C/PCIe/PMIC/QSPI/USB

* tag 'spacemit-dt-for-7.2-1' of https://github.com/spacemit-com/linux: (35 commits)
  riscv: dts: spacemit: enable PMIC on OrangePi R2S
  dts: riscv: spacemit: k3: Fix I/O power settings
  riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores
  riscv: dts: spacemit: k3: Initial support for CoM260-IFX board
  dt-bindings: riscv: spacemit: Add K3 CoM260-IFX board
  riscv: dts: spacemit: k1-musepi-pro: add SD card support with UHS modes
  riscv: dts: spacemit: k3: Add pwm support
  riscv: dts: spacemit: fix uboot partition offset on Milk-V Jupiter
  riscv: dts: spacemit: enable SD card support on Milk-V Jupiter
  riscv: dts: spacemit: enable eMMC on Milk-V Jupiter
  riscv: dts: spacemit: sort aliases on Milk-V Jupiter
  riscv: dts: spacemit: set console baud rate on Milk-V Jupiter
  riscv: dts: spacemit: enable USB3 on OrangePi R2S
  riscv: dts: spacemit: Add thermal sensor for K1 SoC
  riscv: dts: spacemit: Add PDMA controller node for K3 SoC
  riscv: dts: spacemit: enable QSPI for OrangePi RV2
  riscv: dts: spacemit: k1-musepi-pro: set default console baud rate
  riscv: dts: spacemit: k1-musepi-pro: enable PCIe ports
  riscv: dts: spacemit: k1-musepi-pro: enable USB 3 ports
  riscv: dts: spacemit: k1-musepi-pro: enable QSPI and add SPI NOR
  ...

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

T-HEAD Devicetrees for 7.2

Enable wifi on two TH1520 boards: BeagleV Ahead and Lichee Pi 4a.

The BeagleV Ahead board uses an AP6203BM WiFi module connected to SDIO1.
The Lichee Pi 4A has an RTL8723DS WiFi module also connected to SDIO1.
The module reset line is driven through a PCA9557 GPIO expander on the
I2C1 bus.

* tag 'thead-dt-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux:
  riscv: dts: thead: Enable wifi on the BeagleV-Ahead
  riscv: dts: thead: Enable WiFi on Lichee Pi 4A
  riscv: dts: thead: Add TH1520 I2C1 controller

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

The SG2042 MSI controller has one 32-bit doorbell register, and each bit
corresponds to an interrupt. At a glance, it seems that the MSI
controller can support 32 interrupts; however the PCI MSI capability
only supports 16-bit messages, which makes the high 16 interrupts
unusable in such way.

Reduce the MSI count to 16 to prevent producing MSI message values that
cannot fit 16-bit integers.

Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox.
Link: https://patch.msgid.link/20260407160143.1182430-1-zhengxingda@iscas.ac.cn
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

Previous the CPU unit address cpu of sg2042 use decimal, it is
not following the general convention for unit addresses of the
OF. Convent the unit address to hex to resolve this problem.

The introduces a small change for the CPU node name, but it should
affect nothing since there is no direct full-path reference to
these CPU nodes.

Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10")
Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox.
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox.
Link: https://patch.msgid.link/20260426013449.694435-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

Previous the CPU unit address cpu of sg2044 use decimal, it is
not following the general convention for unit addresses of the
OF. Convent the unit address to hex to resolve this problem.

The introduces a small change for the CPU node name, but it should
nothing since there is no direct full-path reference to these
CPU nodes.

Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://patch.msgid.link/20260426013449.694435-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all
four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent
so the kernel uses coherent DMA mappings instead of non-coherent bounce
buffering.

Cc: stable@vger.kernel.org
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Link: https://patch.msgid.link/20260331171248.973014-3-gaohan@iscas.ac.cn
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>