<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/arch/powerpc/sysdev, branch v3.11.2</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>Merge remote-tracking branch 'scott/next' into next</title>
<updated>2013-07-02T07:42:17+00:00</updated>
<author>
<name>Benjamin Herrenschmidt</name>
<email>benh@kernel.crashing.org</email>
</author>
<published>2013-07-02T07:42:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=dd8164c1dd7f511aa362f548fd8c4882bee3fd54'/>
<id>dd8164c1dd7f511aa362f548fd8c4882bee3fd54</id>
<content type='text'>
Merge Freescale updates
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Merge Freescale updates
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/fsl: add MPIC timer wakeup support</title>
<updated>2013-07-01T23:38:42+00:00</updated>
<author>
<name>Dongsheng.wang@freescale.com</name>
<email>Dongsheng.wang@freescale.com</email>
</author>
<published>2013-04-09T02:22:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=a63b3bc7db32b63bfe5f48fa8582f931db81c86e'/>
<id>a63b3bc7db32b63bfe5f48fa8582f931db81c86e</id>
<content type='text'>
The driver provides a way to wake up the system by the MPIC timer.

For example,
echo 5 &gt; /sys/devices/system/mpic/timer_wakeup
echo standby &gt; /sys/power/state

After 5 seconds the MPIC timer will generate an interrupt to wake up
the system.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Zhao Chenhui &lt;chenhui.zhao@freescale.com&gt;
Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The driver provides a way to wake up the system by the MPIC timer.

For example,
echo 5 &gt; /sys/devices/system/mpic/timer_wakeup
echo standby &gt; /sys/power/state

After 5 seconds the MPIC timer will generate an interrupt to wake up
the system.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Zhao Chenhui &lt;chenhui.zhao@freescale.com&gt;
Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpic: create mpic subsystem object</title>
<updated>2013-07-01T23:38:42+00:00</updated>
<author>
<name>Dongsheng.wang@freescale.com</name>
<email>Dongsheng.wang@freescale.com</email>
</author>
<published>2013-04-09T02:22:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=9e6f31a9dbc58f6a5661f8dc8c919441b8d3ced4'/>
<id>9e6f31a9dbc58f6a5661f8dc8c919441b8d3ced4</id>
<content type='text'>
Register a mpic subsystem at /sys/devices/system/

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Register a mpic subsystem at /sys/devices/system/

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpic: add global timer support</title>
<updated>2013-07-01T23:38:41+00:00</updated>
<author>
<name>Dongsheng.wang@freescale.com</name>
<email>Dongsheng.wang@freescale.com</email>
</author>
<published>2013-04-09T02:22:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=36ca09be6ff77a4e5b54b8b68ed7be7aa184250b'/>
<id>36ca09be6ff77a4e5b54b8b68ed7be7aa184250b</id>
<content type='text'>
The MPIC global timer is a hardware timer inside the Freescale PIC complying
with OpenPIC standard. When the specified interval times out, the hardware
timer generates an interrupt. The driver currently is only tested on fsl chip,
but it can potentially support other global timers complying to OpenPIC
standard.

The two independent groups of global timer on fsl chip, group A and group B,
are identical in their functionality, except that they appear at different
locations within the PIC register map. The hardware timer can be cascaded to
create timers larger than the default 31-bit global timers. Timer cascade
fields allow configuration of up to two 63-bit timers. But These two groups
of timers cannot be cascaded together.

It can be used as a wakeup source for low power modes. It also could be used
as periodical timer for protocols, drivers and etc.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The MPIC global timer is a hardware timer inside the Freescale PIC complying
with OpenPIC standard. When the specified interval times out, the hardware
timer generates an interrupt. The driver currently is only tested on fsl chip,
but it can potentially support other global timers complying to OpenPIC
standard.

The two independent groups of global timer on fsl chip, group A and group B,
are identical in their functionality, except that they appear at different
locations within the PIC register map. The hardware timer can be cascaded to
create timers larger than the default 31-bit global timers. Timer cascade
fields allow configuration of up to two 63-bit timers. But These two groups
of timers cannot be cascaded together.

It can be used as a wakeup source for low power modes. It also could be used
as periodical timer for protocols, drivers and etc.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpic: add irq_set_wake support</title>
<updated>2013-07-01T23:38:41+00:00</updated>
<author>
<name>Dongsheng.wang@freescale.com</name>
<email>Dongsheng.wang@freescale.com</email>
</author>
<published>2013-04-09T02:22:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=5ff04b7287d87c1db74f47360365905ed9a97ff7'/>
<id>5ff04b7287d87c1db74f47360365905ed9a97ff7</id>
<content type='text'>
Add irq_set_wake support. Just add IRQF_NO_SUSPEND to desc-&gt;action-&gt;flag.
So the wake up interrupt will not be disable in suspend_device_irqs.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add irq_set_wake support. Just add IRQF_NO_SUSPEND to desc-&gt;action-&gt;flag.
So the wake up interrupt will not be disable in suspend_device_irqs.

Signed-off-by: Wang Dongsheng &lt;dongsheng.wang@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpic: Add get_version API both for internal and external use</title>
<updated>2013-07-01T23:38:28+00:00</updated>
<author>
<name>Hongtao Jia</name>
<email>hongtao.jia@freescale.com</email>
</author>
<published>2013-04-10T02:52:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=86d379690c3b005418fafc9afdcdfc731a043862'/>
<id>86d379690c3b005418fafc9afdcdfc731a043862</id>
<content type='text'>
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.

Signed-off-by: Jia Hongtao &lt;hongtao.jia@freescale.com&gt;
Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.

Signed-off-by: Jia Hongtao &lt;hongtao.jia@freescale.com&gt;
Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'v3.10' into next</title>
<updated>2013-07-01T07:57:25+00:00</updated>
<author>
<name>Benjamin Herrenschmidt</name>
<email>benh@kernel.crashing.org</email>
</author>
<published>2013-07-01T07:57:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=24a72acac155576d630cf4304fa9cefb9b62ea1f'/>
<id>24a72acac155576d630cf4304fa9cefb9b62ea1f</id>
<content type='text'>
Merge 3.10 in order to get some of the last minute powerpc
changes, resolve conflicts and add additional fixes on top
of them.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Merge 3.10 in order to get some of the last minute powerpc
changes, resolve conflicts and add additional fixes on top
of them.
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/pci: Fix boot panic on mpc83xx (regression)</title>
<updated>2013-06-24T21:54:09+00:00</updated>
<author>
<name>Rojhalat Ibrahim</name>
<email>imr@rtschenk.de</email>
</author>
<published>2013-06-17T14:02:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=b37e161388ac3980d5dfb73050e85874b84253eb'/>
<id>b37e161388ac3980d5dfb73050e85874b84253eb</id>
<content type='text'>
The following commit caused a fatal oops when booting on mpc83xx with
a non-express PCI bus (regardless of whether a PCI device is present):

commit 50d8f87d2b39313dae9d0a2d9b23d377328f2f7b
Author: Rojhalat Ibrahim &lt;imr@rtschenk.de&gt;
Date:   Mon Apr 8 10:15:28 2013 +0200

    powerpc/fsl-pci Make PCIe hotplug work with Freescale PCIe controllers

    Up to now the PCIe link status on Freescale PCIe controllers was only
    checked once at boot time. So hotplug did not work. With this patch the
    link status is checked on every config read. PCIe devices not present at
    boot time are found after doing 'echo 1 &gt;/sys/bus/pci/rescan'.

    Signed-off-by: Rojhalat Ibrahim &lt;imr@rtschenk.de&gt;
    Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;

This patch fixes the issue by calling setup_indirect_pci for all device types.
fsl_indirect_read_config is now only used for booke/86xx PCIe controllers.

Reported-by: Michael Guntsche &lt;mike@it-loops.com&gt;
Cc: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Rojhalat Ibrahim &lt;imr@rtschenk.de&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The following commit caused a fatal oops when booting on mpc83xx with
a non-express PCI bus (regardless of whether a PCI device is present):

commit 50d8f87d2b39313dae9d0a2d9b23d377328f2f7b
Author: Rojhalat Ibrahim &lt;imr@rtschenk.de&gt;
Date:   Mon Apr 8 10:15:28 2013 +0200

    powerpc/fsl-pci Make PCIe hotplug work with Freescale PCIe controllers

    Up to now the PCIe link status on Freescale PCIe controllers was only
    checked once at boot time. So hotplug did not work. With this patch the
    link status is checked on every config read. PCIe devices not present at
    boot time are found after doing 'echo 1 &gt;/sys/bus/pci/rescan'.

    Signed-off-by: Rojhalat Ibrahim &lt;imr@rtschenk.de&gt;
    Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;

This patch fixes the issue by calling setup_indirect_pci for all device types.
fsl_indirect_read_config is now only used for booke/86xx PCIe controllers.

Reported-by: Michael Guntsche &lt;mike@it-loops.com&gt;
Cc: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Rojhalat Ibrahim &lt;imr@rtschenk.de&gt;
Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: Mark low level irq handlers NO_THREAD</title>
<updated>2013-06-20T06:55:08+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2013-02-13T22:38:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=e80034047bee9ceacfc1bfff873ebfdd049817ca'/>
<id>e80034047bee9ceacfc1bfff873ebfdd049817ca</id>
<content type='text'>
These low level handlers cannot be threaded. Mark them NO_THREAD

Reported-by: leroy christophe &lt;christophe.leroy@c-s.fr&gt;
Tested-by: leroy christophe &lt;christophe.leroy@c-s.fr&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
These low level handlers cannot be threaded. Mark them NO_THREAD

Reported-by: leroy christophe &lt;christophe.leroy@c-s.fr&gt;
Tested-by: leroy christophe &lt;christophe.leroy@c-s.fr&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpic: Fix irq distribution problem when MPIC_SINGLE_DEST_CPU</title>
<updated>2013-05-31T22:29:24+00:00</updated>
<author>
<name>chenhui zhao</name>
<email>chenhui.zhao@freescale.com</email>
</author>
<published>2013-05-27T21:59:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=e242114afff0a41550e174cd787cdbafd34625de'/>
<id>e242114afff0a41550e174cd787cdbafd34625de</id>
<content type='text'>
For the mpic with a flag MPIC_SINGLE_DEST_CPU, only one bit should be
set in interrupt destination registers.

The code is applicable to 64-bit platforms as well as 32-bit.

Signed-off-by: Zhao Chenhui &lt;chenhui.zhao@freescale.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For the mpic with a flag MPIC_SINGLE_DEST_CPU, only one bit should be
set in interrupt destination registers.

The code is applicable to 64-bit platforms as well as 32-bit.

Signed-off-by: Zhao Chenhui &lt;chenhui.zhao@freescale.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
