linux-stable.git/arch/powerpc/kernel/exceptions-64e.S, branch v3.2

powerpc/book3e-64: Reraise doorbell when masked by soft-irq-disable

2011-06-29T06:40:59+00:00

Signed-off-by: Scott Wood 
Signed-off-by: Benjamin Herrenschmidt

powerpc/e5500: set non-base IVORs

2011-05-19T05:36:43+00:00

Without this, we attempt to use doorbells for IPIs, and end up
branching to some bad address.  Plus, even for the exceptions
we don't implement, it's good to handle it and get a message out.

Signed-off-by: Scott Wood 
Signed-off-by: Kumar Gala

powerpc/fsl-booke64: Add support for Debug Level exception handler

2011-05-19T05:36:42+00:00

Signed-off-by: Kumar Gala

powerpc: Add early debug for WSP platforms

2011-05-06T03:32:41+00:00

Signed-off-by: Jack Miller 
Signed-off-by: Michael Ellerman 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Add WSP platform

2011-05-06T03:32:35+00:00

Add a platform for the Wire Speed Processor, based on the PPC A2.

This includes code for the ICS & OPB interrupt controllers, as well
as a SCOM backend, and SCOM based cpu bringup.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: David Gibson 
Signed-off-by: Jack Miller 
Signed-off-by: Ian Munsie 
Signed-off-by: Michael Ellerman 
Signed-off-by: Benjamin Herrenschmidt

powerpc/book3e: Flush IPROT protected TLB entries leftover by firmware

2011-04-27T03:02:16+00:00

When we set up the TLB for ourselves on Book3E, we need to flush out any
old mappings established by the firmware or bootloader.  At present we
attempt this with a tlbilx to flush everything, but this will leave behind
any entries with the IPROT bit set.

There are several good reason firmware might establish mappings with IPROT,
and in fact ePAPR compliant firmwares are required to establish their
initial mapped area with IPROT.

This patch, therefore adds more complex code to scan through the TLB upon
entry and flush away any entries that are not our own.

Signed-off-by: Jack Miller 
Signed-off-by: David Gibson 
Signed-off-by: Michael Ellerman 
Signed-off-by: Benjamin Herrenschmidt

powerpc/book3e: Use way 3 for linear mapping bolted entry

2011-04-27T03:02:14+00:00

An erratum on A2 can lead to the bolted entry we insert for the linear
mapping being evicted, to avoid that write the bolted entry to way 3.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Michael Ellerman 
Signed-off-by: Benjamin Herrenschmidt

Fix common misspellings

2011-03-31T14:26:23+00:00

Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi

powerpc/book3e: Fix single step when using HW page tables

2010-07-14T04:13:51+00:00

We patch the TLB miss exception vectors to point to alternate
functions when using HW page table on BookE.

However, we were patching in a new branch in the first instruction
of the exception handler instead of the second one, thus overriding
the nop that is in the first instruction.

This cause problems when single stepping as we rely on that nop for
the single step to stop properly within the exception vector range
rather than on the target of the branch.

Signed-off-by: Benjamin Herrenschmidt

powerpc/book3e: Add generic 64-bit idle powersave support

2010-07-14T04:13:18+00:00

We use a similar technique to ppc32: We set a thread local flag
to indicate that we are about to enter or have entered the stop
state, and have fixup code in the async interrupt entry code that
reacts to this flag to make us return to a different location
(sets NIP to LINK in our case).

Signed-off-by: Benjamin Herrenschmidt 
--
v2. Fix lockdep bug
    Re-mask interrupts when coming back from idle