<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/arch/powerpc/kernel/cputable.c, branch linux-2.6.36.y</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>powerpc/47x: Remove redundant line from cputable.c</title>
<updated>2010-08-23T11:37:01+00:00</updated>
<author>
<name>Dave Kleikamp</name>
<email>shaggy@linux.vnet.ibm.com</email>
</author>
<published>2010-08-18T06:44:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=66477466b8b79c98af17f1c2267596c8b6b4b561'/>
<id>66477466b8b79c98af17f1c2267596c8b6b4b561</id>
<content type='text'>
There are two entries for .cpu_user_features in
arch/powerpc/kernel/cputable.c.  Remove the one that doesn't belong

Signed-off-by: Dave Kleikamp &lt;shaggy@linux.vnet.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There are two entries for .cpu_user_features in
arch/powerpc/kernel/cputable.c.  Remove the one that doesn't belong

Signed-off-by: Dave Kleikamp &lt;shaggy@linux.vnet.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/40x: Distinguish AMCC PowerPC 405EX and 405EXr correctly</title>
<updated>2010-07-26T13:07:24+00:00</updated>
<author>
<name>Lee Nipper</name>
<email>lee.nipper@gmail.com</email>
</author>
<published>2010-07-09T01:17:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=ff349103964d43c28b7b80bdecf7ace0113b3dda'/>
<id>ff349103964d43c28b7b80bdecf7ace0113b3dda</id>
<content type='text'>
The recent AMCC 405EX Rev D without Security uses a PVR value
that matches the old 405EXr Rev A/B with Security.
The 405EX Rev D without Security would be shown
incorrectly as an 405EXr. The pvr_mask of 0xffff0004
is no longer sufficient to distinguish the 405EX from 405EXr.

This patch replaces 2 entries in the cpu_specs table
and adds 8 more, each using pvr_mask of 0xffff000f
and appropriate pvr_value to distinguish the AMCC
PowerPC 405EX and 405EXr instances.
The cpu_name for these entries now includes the
Rev, in similar fashion to the 440GX.

Signed-off-by: Lee Nipper &lt;lee.nipper@gmail.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The recent AMCC 405EX Rev D without Security uses a PVR value
that matches the old 405EXr Rev A/B with Security.
The 405EX Rev D without Security would be shown
incorrectly as an 405EXr. The pvr_mask of 0xffff0004
is no longer sufficient to distinguish the 405EX from 405EXr.

This patch replaces 2 entries in the cpu_specs table
and adds 8 more, each using pvr_mask of 0xffff000f
and appropriate pvr_value to distinguish the AMCC
PowerPC 405EX and 405EXr instances.
The cpu_name for these entries now includes the
Rev, in similar fashion to the 440GX.

Signed-off-by: Lee Nipper &lt;lee.nipper@gmail.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/e500mc: Implement machine check handler.</title>
<updated>2010-05-21T12:41:52+00:00</updated>
<author>
<name>Scott Wood</name>
<email>scottwood@freescale.com</email>
</author>
<published>2010-04-08T05:38:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=fe04b1121511a97982a1fcdd38e44d2029304a6d'/>
<id>fe04b1121511a97982a1fcdd38e44d2029304a6d</id>
<content type='text'>
Most of the MSCR bit assigments are different in e500mc versus
e500, and they are now write-one-to-clear.

Some e500mc machine check conditions are made recoverable (as long as
they aren't stuck on), most notably L1 instruction cache parity errors.

Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Most of the MSCR bit assigments are different in e500mc versus
e500, and they are now write-one-to-clear.

Some e500mc machine check conditions are made recoverable (as long as
they aren't stuck on), most notably L1 instruction cache parity errors.

Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/4xx: Simple platform for the ISS 4xx simulator</title>
<updated>2010-05-05T15:11:56+00:00</updated>
<author>
<name>Torez Smith</name>
<email>lnxtorez@linux.vnet.ibm.com</email>
</author>
<published>2010-03-05T10:45:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=b4e8c8dd8456c1d3685fb5b715c9795d250f500e'/>
<id>b4e8c8dd8456c1d3685fb5b715c9795d250f500e</id>
<content type='text'>
This is a trivial 4xx plaform that uses the new simple bsp from
Josh and is handy to use in simulators such as ISS or even Mambo
who don't properly implement most of the actual devices in the
SoC but really only the core.

Signed-off-by: Torez Smith  &lt;lnxtorez@linux.vnet.ibm.com&gt;
Signed-off-by: Dave Kleikamp &lt;shaggy@linux.vnet.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is a trivial 4xx plaform that uses the new simple bsp from
Josh and is handy to use in simulators such as ISS or even Mambo
who don't properly implement most of the actual devices in the
SoC but really only the core.

Signed-off-by: Torez Smith  &lt;lnxtorez@linux.vnet.ibm.com&gt;
Signed-off-by: Dave Kleikamp &lt;shaggy@linux.vnet.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/476: add machine check handler for 47x core</title>
<updated>2010-05-05T13:27:22+00:00</updated>
<author>
<name>Dave Kleikamp</name>
<email>shaggy@linux.vnet.ibm.com</email>
</author>
<published>2010-03-05T03:43:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=fc5e709731429bc2db27897630e7c0089f297680'/>
<id>fc5e709731429bc2db27897630e7c0089f297680</id>
<content type='text'>
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.

Signed-off-by: Dave Kleikamp &lt;shaggy@linux.vnet.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The 47x core's MCSR varies from 44x, so it needs it's own machine check
handler.

Signed-off-by: Dave Kleikamp &lt;shaggy@linux.vnet.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/47x: Base ppc476 support</title>
<updated>2010-05-05T13:11:10+00:00</updated>
<author>
<name>Dave Kleikamp</name>
<email>shaggy@linux.vnet.ibm.com</email>
</author>
<published>2010-03-05T10:43:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=e7f75ad01d590243904c2d95ab47e6b2e9ef6dad'/>
<id>e7f75ad01d590243904c2d95ab47e6b2e9ef6dad</id>
<content type='text'>
This patch adds the base support for the 476 processor.  The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.

The goal is to have a single binary that will run on 44x and 47x, but
we still have some details to work out.  The biggest is that the L1 cache
line size differs on the two platforms, but it's currently a compile-time
option.

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Torez Smith  &lt;lnxtorez@linux.vnet.ibm.com&gt;
Signed-off-by: Dave Kleikamp &lt;shaggy@linux.vnet.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds the base support for the 476 processor.  The code was
primarily written by Ben Herrenschmidt and Torez Smith, but I've been
maintaining it for a while.

The goal is to have a single binary that will run on 44x and 47x, but
we still have some details to work out.  The biggest is that the L1 cache
line size differs on the two platforms, but it's currently a compile-time
option.

Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Torez Smith  &lt;lnxtorez@linux.vnet.ibm.com&gt;
Signed-off-by: Dave Kleikamp &lt;shaggy@linux.vnet.ibm.com&gt;
Signed-off-by: Josh Boyer &lt;jwboyer@linux.vnet.ibm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/perf: e500 support</title>
<updated>2010-03-05T09:04:08+00:00</updated>
<author>
<name>Scott Wood</name>
<email>scottwood@freescale.com</email>
</author>
<published>2010-02-26T00:09:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=a11106544f33c104706ae42d27219a409b67478e'/>
<id>a11106544f33c104706ae42d27219a409b67478e</id>
<content type='text'>
This implements perf_event support for the Freescale embedded performance
monitor, based on the existing perf_event.c that supports server/classic
chips.

Some limitations:
- Performance monitor interrupts are regular EE interrupts, and thus you
  can't profile places with interrupts disabled.  We may want to implement
  soft IRQ-disabling, with perfmon interrupts exempted and treated as NMIs.
- When trying to schedule multiple event groups at once, and using
  restricted events, situations could arise where scheduling fails even
  though it would be possible.  Consider three groups, each with two events.
  One group has restricted events, the others don't.  The two non-restricted
  groups are scheduled, then one is removed, which happens to occupy the two
  counters that can't do restricted events.  The remaining non-restricted
  group will not be moved to the non-restricted-capable counters to make
  room if the restricted group tries to be scheduled.

Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
Acked-by: Paul Mackerras &lt;paulus@samba.org&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This implements perf_event support for the Freescale embedded performance
monitor, based on the existing perf_event.c that supports server/classic
chips.

Some limitations:
- Performance monitor interrupts are regular EE interrupts, and thus you
  can't profile places with interrupts disabled.  We may want to implement
  soft IRQ-disabling, with perfmon interrupts exempted and treated as NMIs.
- When trying to schedule multiple event groups at once, and using
  restricted events, situations could arise where scheduling fails even
  though it would be possible.  Consider three groups, each with two events.
  One group has restricted events, the others don't.  The two non-restricted
  groups are scheduled, then one is removed, which happens to occupy the two
  counters that can't do restricted events.  The remaining non-restricted
  group will not be moved to the non-restricted-capable counters to make
  room if the restricted group tries to be scheduled.

Signed-off-by: Scott Wood &lt;scottwood@freescale.com&gt;
Acked-by: Paul Mackerras &lt;paulus@samba.org&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc: broadway processor support</title>
<updated>2009-12-13T05:24:29+00:00</updated>
<author>
<name>Albert Herranz</name>
<email>albert_herranz@yahoo.es</email>
</author>
<published>2009-12-12T06:31:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=45158dc7d68972de919c24130b784b548df06546'/>
<id>45158dc7d68972de919c24130b784b548df06546</id>
<content type='text'>
This patch extends the cputable entry of the 750CL to also match
the 750CL-based "Broadway" cpu found on the Nintendo Wii.

As of this patch, the following "Broadway" design revision levels have
been seen in the wild:
- DD1.2 (87102)
- DD2.0 (87200)

Signed-off-by: Albert Herranz &lt;albert_herranz@yahoo.es&gt;
Acked-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch extends the cputable entry of the 750CL to also match
the 750CL-based "Broadway" cpu found on the Nintendo Wii.

As of this patch, the following "Broadway" design revision levels have
been seen in the wild:
- DD1.2 (87102)
- DD2.0 (87200)

Signed-off-by: Albert Herranz &lt;albert_herranz@yahoo.es&gt;
Acked-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/oprofile: Add ppc750 CL as supported by oprofile</title>
<updated>2009-10-14T05:58:39+00:00</updated>
<author>
<name>Dragos Tatulea</name>
<email>dtatulea@ixiacom.com</email>
</author>
<published>2009-09-16T08:58:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=04f5653477a245379da9fa57dd7d1b4b75dd4b0b'/>
<id>04f5653477a245379da9fa57dd7d1b4b75dd4b0b</id>
<content type='text'>
Here's a patch that adds the ppc750 CL cpu as supported by oprofile.

Signed-off-by: Dragos Tatulea &lt;dtatulea@ixiacom.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Here's a patch that adds the ppc750 CL cpu as supported by oprofile.

Signed-off-by: Dragos Tatulea &lt;dtatulea@ixiacom.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/book3e-64: Move the default cpu table entry</title>
<updated>2009-08-28T04:24:13+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2009-08-18T19:08:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=f45c4486f70d0a6502e7499a8664cdc0bba84cd2'/>
<id>f45c4486f70d0a6502e7499a8664cdc0bba84cd2</id>
<content type='text'>
Move the default cpu entry table for CONFIG_PPC_BOOK3E_64 to the
very end since we will probably want to support both 32-bit and
64-bit kernels for some processors that are higher up in the list.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move the default cpu entry table for CONFIG_PPC_BOOK3E_64 to the
very end since we will probably want to support both 32-bit and
64-bit kernels for some processors that are higher up in the list.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
