linux-stable.git/arch/powerpc/kernel/cpu_setup_power7.S, branch v3.0 Linux kernel stable tree powerpc: Initialize TLB and LPID register on HV mode Power7 2011-04-20T01:03:24+00:00 Benjamin Herrenschmidt benh@kernel.crashing.org 2011-03-01T04:46:09+00:00 b144871cb5f2c268e94258ae8f1ec810db2e1120 In case entry from the bootloader isn't "clean" Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 
In case entry from the bootloader isn't "clean"

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
powerpc: Initialize LPCR:DPFD on power7 to a sane default 2011-04-20T01:03:23+00:00 Benjamin Herrenschmidt benh@kernel.crashing.org 2011-01-24T02:25:55+00:00 895796a8ab548fe03b6fea410dcb1b86e1913708 This sets the default data stream prefetch size for operating systems that don't set their own value in DSCR. We use 4 which is "medium". Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 
This sets the default data stream prefetch size for operating
systems that don't set their own value in DSCR. We use 4 which
is "medium".

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
powerpc: Base support for exceptions using HSRR0/1 2011-04-20T01:03:22+00:00 Benjamin Herrenschmidt benh@kernel.crashing.org 2011-04-05T04:20:31+00:00 a5d4f3ad3a28cf046836b9bfae61d532b8f77036 Pass the register type to the prolog, also provides alternate "HV" version of hardware interrupt (0x500) and adjust LPES accordingly We tag those interrupts by setting bit 0x2 in the trap number Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 
Pass the register type to the prolog, also provides alternate "HV"
version of hardware interrupt (0x500) and adjust LPES accordingly

We tag those interrupts by setting bit 0x2 in the trap number

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
powerpc: Define CPU feature for Architected 2.06 HV mode 2011-04-20T01:03:22+00:00 Benjamin Herrenschmidt benh@kernel.crashing.org 2011-01-20T07:50:55+00:00 24cc67de62eebbda3ce0c46bdd56582c00dccd03 This bit indicates that we are operating in hypervisor mode on a CPU compliant to architecture 2.06 or later (currently server only). We set it on POWER7 and have a boot-time CPU setup function that clears it if MSR:HV isn't set (booting under a hypervisor). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> 
This bit indicates that we are operating in hypervisor mode on a CPU
compliant to architecture 2.06 or later (currently server only).

We set it on POWER7 and have a boot-time CPU setup function that
clears it if MSR:HV isn't set (booting under a hypervisor).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>