linux-stable.git/arch/powerpc/kernel/cpu_setup_power.S, branch linux-4.7.y

powerpc/mm: Move hash related mmu-*.h headers to book3s/

2016-03-03T10:19:21+00:00

No code changes.

Signed-off-by: Aneesh Kumar K.V 
Signed-off-by: Michael Ellerman

powerpc: Add POWER9 cputable entry

2016-02-22T09:47:48+00:00

Add a cputable entry for POWER9.  More code is required to actually
boot and run on a POWER9 but this gets the base piece in which we can
start building on.

Copies over from POWER8 except for:
- Adds a new CPU_FTR_ARCH_300 bit to start hanging new architecture
   features from (in subsequent patches).
- Advertises new user features bits PPC_FEATURE2_ARCH_3_00 &
  HAS_IEEE128 when on POWER9.
- Drops CPU_FTR_SUBCORE.
- Drops PMU code and machine check.

Signed-off-by: Michael Neuling 
Signed-off-by: Michael Ellerman

powerpc: Use defines for __init_tlb_power[78]

2016-02-22T09:47:47+00:00

Use defines for literals __init_tlb_power[78] rather than hand coding
them.

Signed-off-by: Michael Neuling 
Signed-off-by: Michael Ellerman

powerpc/book3s: Fix flush_tlb cpu_spec hook to take a generic argument.

2015-03-16T20:52:48+00:00

The flush_tlb hook in cpu_spec was introduced as a generic function hook
to invalidate TLBs. But the current implementation of flush_tlb hook
takes IS (invalidation selector) as an argument which is architecture
dependent. Hence, It is not right to have a generic routine where caller
has to pass non-generic argument.

This patch fixes this and makes flush_tlb hook as high level API.

Reported-by: Benjamin Herrenschmidt 
Signed-off-by: Mahesh Salgaonkar 
Signed-off-by: Michael Ellerman

powerpc/powernv: Enable POWER8 doorbell IPIs

2014-06-11T07:05:12+00:00

This patch enables POWER8 doorbell IPIs on powernv.

Since doorbells can only IPI within a core, we test to see when we can use
doorbells and if not we fall back to XICS.  This also enables hypervisor
doorbells to wakeup us up from nap/sleep via the LPCR PECEDH bit.

Based on tests by Anton, the best case IPI latency between two threads dropped
from 894ns to 512ns.

Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc/ppc64: Do not turn AIL (reloc-on interrupts) too early

2014-04-07T00:33:15+00:00

Turn them on at the same time as we allow MSR_IR/DR in the paca
kernel MSR, ie, after the MMU has been setup enough to be able
to handle relocated access to the linear mapping.

Signed-off-by: Benjamin Herrenschmidt

powerpc/book3s: Add flush_tlb operation in cpu_spec.

2013-12-05T05:04:38+00:00

This patch introduces flush_tlb operation in cpu_spec structure. This will
help us to invoke appropriate CPU-side flush tlb routine. This patch
adds the foundation to invoke CPU specific flush routine for respective
architectures. Currently this patch introduce flush_tlb for p7 and p8.

Signed-off-by: Mahesh Salgaonkar 
Acked-by: Paul Mackerras 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Fix TLB cleanup at boot on POWER8

2013-05-24T08:13:44+00:00

The TLB has 512 congruence classes (2048 entries 4 way set associative)
while P7 had 128

Signed-off-by: Benjamin Herrenschmidt

powerpc: Turn on the EBB H/FSCR bits

2013-05-02T00:36:55+00:00

This turns Event Based Branching (EBB) on in the Hypervisor Facility Status and
Control Register (HFSCR) and Facility Status and Control Register (FSCR).

Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Setup BHRB instructions facility in HFSCR for POWER8

2013-05-02T00:35:15+00:00

Make BHRB instructions available in problem and privileged states.

Signed-off-by: Anshuman Khandual 
Signed-off-by: Benjamin Herrenschmidt