linux-stable.git/arch/powerpc/kernel/align.c, branch linux-3.12.y

powerpc: Don't try to fix up misaligned load-with-reservation instructions

2017-04-27T17:34:55+00:00

commit 48fe9e9488743eec9b7c1addd3c93f12f2123d54 upstream.

In the past, there was only one load-with-reservation instruction,
lwarx, and if a program attempted a lwarx on a misaligned address, it
would take an alignment interrupt and the kernel handler would emulate
it as though it was lwzx, which was not really correct, but benign since
it is loading the right amount of data, and the lwarx should be paired
with a stwcx. to the same address, which would also cause an alignment
interrupt which would result in a SIGBUS being delivered to the process.

We now have 5 different sizes of load-with-reservation instruction. Of
those, lharx and ldarx cause an immediate SIGBUS by luck since their
entries in aligninfo[] overlap instructions which were not fixed up, but
lqarx overlaps with lhz and will be emulated as such. lbarx can never
generate an alignment interrupt since it only operates on 1 byte.

To straighten this out and fix the lqarx case, this adds code to detect
the l[hwdq]arx instructions and return without fixing them up, resulting
in a SIGBUS being delivered to the process.

[js] include disassemble.h in 3.12

Signed-off-by: Paul Mackerras 
Signed-off-by: Michael Ellerman 
Signed-off-by: Jiri Slaby

powerpc: Never handle VSX alignment exceptions from kernel

2013-08-27T04:44:26+00:00

The VSX alignment handler needs to write out the existing VSX
state to memory before operating on it (flush_vsx_to_thread()).
If we take a VSX alignment exception in the kernel bad things
will happen. It looks like we could write the kernel state out
to the user process, or we could handle the kernel exception
using data from the user process (depending if MSR_VSX is set
or not).

Worse still, if the code to read or write the VSX state causes an
alignment exception, we will recurse forever. I ended up with
hundreds of megabytes of kernel stack to look through as a result.

Floating point and SPE code have similar issues but already include
a user check. Add the same check to emulate_vsx().

With this patch any unaligned VSX loads and stores in the kernel
will show up as a clear oops rather than silent corruption of
kernel or userspace VSX state, or worse, corruption of a potentially
unlimited amount of kernel memory.

Signed-off-by: Anton Blanchard 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Handle unaligned ldbrx/stdbrx

2013-08-14T01:50:20+00:00

Normally when we haven't implemented an alignment handler for
a load or store instruction the process will be terminated.

The alignment handler uses the DSISR (or a pseudo one) to locate
the right handler. Unfortunately ldbrx and stdbrx overlap lfs and
stfs so we incorrectly think ldbrx is an lfs and stdbrx is an
stfs.

This bug is particularly nasty - instead of terminating the
process we apply an incorrect fixup and continue on.

With more and more overlapping instructions we should stop
creating a pseudo DSISR and index using the instruction directly,
but for now add a special case to catch ldbrx/stdbrx.

Signed-off-by: Anton Blanchard 
Cc: 
Signed-off-by: Benjamin Herrenschmidt

Disintegrate asm/system.h for PowerPC

2012-03-28T17:30:02+00:00

Disintegrate asm/system.h for PowerPC.

Signed-off-by: David Howells 
Acked-by: Benjamin Herrenschmidt 
cc: linuxppc-dev@lists.ozlabs.org

powerpc: Remove fpscr use from [kvm_]cvt_{fd,df}

2010-09-02T04:07:32+00:00

Neither lfs nor stfs touch the fpscr, so remove the restore/save of it
around them.

Signed-off-by: Andreas Schwab 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Handle VSX alignment faults correctly in little-endian mode

2009-12-18T03:55:43+00:00

This patch fixes the handling of VSX alignment faults in little-endian
mode (the current code assumes the processor is in big-endian mode).

The patch also makes the handlers clear the top 8 bytes of the register
when handling an 8 byte VSX load.

This is based on 2.6.32.

Signed-off-by: Neil Campbell 
Cc: 
Acked-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Create PPC_WARN_ALIGNMENT to match PPC_WARN_EMULATED

2009-10-28T05:13:03+00:00

perf_event wants a separate event for alignment and emulation faults,
so create another emulation event.  This will make it easy to hook in
perf_event at one spot.

We pass in regs which will be required for these events.

Signed-off-by: Anton Blanchard 
Signed-off-by: Paul Mackerras

powerpc: Keep track of emulated instructions

2009-05-21T05:44:26+00:00

If CONFIG_PPC_EMULATED_STATS is enabled, make available counters for the
various classes of emulated instructions under
/sys/kernel/debug/powerpc/emulated_instructions/ (assumed debugfs is mounted on
/sys/kernel/debug).  Optionally (controlled by
/sys/kernel/debug/powerpc/emulated_instructions/do_warn), rate-limited warnings
can be printed to the console when instructions are emulated.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Fix load/store float double alignment handler

2009-02-23T04:53:05+00:00

When we introduced VSX, we changed the way FPRs are stored in the
thread_struct.  Unfortunately we missed the load/store float double
alignment handler code when updating how we access FPRs in the
thread_struct.

Below fixes this and merges the little/big endian case.

Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Add alignment handler for new lfiwzx instruction

2009-02-23T04:53:04+00:00

lfiwzx is a new floating point load instruction in 2.06 that needs an
alignment handler for Linux.

Turns out to be the worlds easiest handler to add.

Signed-off-by: Michael Neuling 
Signed-off-by: Benjamin Herrenschmidt