<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/arch/powerpc/boot, branch linux-3.6.y</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>powerpc/p4080ds: dts - add usb controller version info and port0</title>
<updated>2012-08-10T12:47:02+00:00</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2012-08-10T10:48:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=09a3017a585eb8567a7de15b426bb1dfb548bf0f'/>
<id>09a3017a585eb8567a7de15b426bb1dfb548bf0f</id>
<content type='text'>
Add the missing usb controller version info and port0, which is
required during setup usb phy.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the missing usb controller version info and port0, which is
required during setup usb phy.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: P3041DS - change espi input-clock from 40MHz to 35MHz</title>
<updated>2012-07-26T13:09:53+00:00</updated>
<author>
<name>Shaohui Xie</name>
<email>Shaohui.Xie@freescale.com</email>
</author>
<published>2012-07-17T07:18:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=e1bd5d8bc13f51c7c991f04255b3868e31933252'/>
<id>e1bd5d8bc13f51c7c991f04255b3868e31933252</id>
<content type='text'>
Default CoreNet Coherency Bus (CCB) frequency on P3041 is 750MHz, but espi
cannot work at 40MHz with this CCB frequency, so we need to slow down the
clock rate of espi to 35MHz to make it work stable at the CCB frequency.

Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Default CoreNet Coherency Bus (CCB) frequency on P3041 is 750MHz, but espi
cannot work at 40MHz with this CCB frequency, so we need to slow down the
clock rate of espi to 35MHz to make it work stable at the CCB frequency.

Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Fix pci base address error for p2020rdb-pc in dts</title>
<updated>2012-07-26T13:09:52+00:00</updated>
<author>
<name>Tang Yuantian</name>
<email>Yuantian.Tang@freescale.com</email>
</author>
<published>2012-07-13T02:27:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=771e6089e3638ea1e06700a9dc4660cd678e35bb'/>
<id>771e6089e3638ea1e06700a9dc4660cd678e35bb</id>
<content type='text'>
Signed-off-by: Tang Yuantian &lt;Yuantian.Tang@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Tang Yuantian &lt;Yuantian.Tang@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Add phy nodes in SGMII mode for MPC8536/44/72DS &amp; P2020DS</title>
<updated>2012-07-12T15:08:09+00:00</updated>
<author>
<name>Jia Hongtao</name>
<email>B38951@freescale.com</email>
</author>
<published>2012-07-12T09:36:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=b915341b4be29b3b2c02da932b69871e9b55ca4b'/>
<id>b915341b4be29b3b2c02da932b69871e9b55ca4b</id>
<content type='text'>
In SGMII riser card different PHY chip are used with different external
IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we
should add another group of PHY nodes for SGMII mode.

For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3.
For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1.
For P2020DS IRQ5 is used for PHY1~PHY2.

Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Jia Hongtao &lt;B38951@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In SGMII riser card different PHY chip are used with different external
IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we
should add another group of PHY nodes for SGMII mode.

For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3.
For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1.
For P2020DS IRQ5 is used for PHY1~PHY2.

Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Jia Hongtao &lt;B38951@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Rename P1021RDB-PC device trees to be consistent</title>
<updated>2012-07-11T12:45:42+00:00</updated>
<author>
<name>Xu Jiucheng</name>
<email>Jiucheng.Xu@freescale.com</email>
</author>
<published>2012-07-10T08:39:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=3ef4106573069775d364a80b962a4d4f9b11a79e'/>
<id>3ef4106573069775d364a80b962a4d4f9b11a79e</id>
<content type='text'>
The board is really P1021RDB-PC, so rename from p1021rdb.* to p1021rdb-pc.*

Signed-off-by: Xu Jiucheng &lt;Jiucheng.Xu@freescale.com&gt;
Signed-off-by: Matthew McClintock &lt;msm@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The board is really P1021RDB-PC, so rename from p1021rdb.* to p1021rdb-pc.*

Signed-off-by: Xu Jiucheng &lt;Jiucheng.Xu@freescale.com&gt;
Signed-off-by: Matthew McClintock &lt;msm@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Add ucc uart support for p1025rdb</title>
<updated>2012-07-10T12:56:45+00:00</updated>
<author>
<name>Zhicheng Fan</name>
<email>B32736@freescale.com</email>
</author>
<published>2012-07-10T07:52:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=b5dc2986879c2a6c65a3cfede7ba6de3531a0f3e'/>
<id>b5dc2986879c2a6c65a3cfede7ba6de3531a0f3e</id>
<content type='text'>
Add device tree nodes to enable ucc uart support on P1025RDB.

Signed-off-by: Zhicheng Fan &lt;B32736@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add device tree nodes to enable ucc uart support on P1025RDB.

Signed-off-by: Zhicheng Fan &lt;B32736@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: MPC8572DS - Update the MSI interrupts into 4-cell format</title>
<updated>2012-07-10T12:08:35+00:00</updated>
<author>
<name>Jia Hongtao</name>
<email>B38951@freescale.com</email>
</author>
<published>2012-07-10T06:08:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=1f0e90ad7a3b6f9f8a0598ed30f4e9c7dd9ff82e'/>
<id>1f0e90ad7a3b6f9f8a0598ed30f4e9c7dd9ff82e</id>
<content type='text'>
With 2-cell format interrupts of MSI PCIe ethernet card can not work.

Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Jia Hongtao &lt;B38951@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With 2-cell format interrupts of MSI PCIe ethernet card can not work.

Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Jia Hongtao &lt;B38951@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: MPC8572DS - Fix eTSEC is not available on core1 of AMP boot</title>
<updated>2012-07-10T12:07:49+00:00</updated>
<author>
<name>Jia Hongtao</name>
<email>B38951@freescale.com</email>
</author>
<published>2012-07-10T06:08:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=a2ec009b7544fdbf1c6b6d624ce0167556247370'/>
<id>a2ec009b7544fdbf1c6b6d624ce0167556247370</id>
<content type='text'>
The issue log on core1 is:
root@mpc8572ds:~# ifconfig eth0 10.192.208.244
net eth0: could not attach to PHY
SIOCSIFFLAGS: No such device

To attach PHY node mdio@24520 should not be disabled in dts of core1.
Because all PHYs are controlled through this node as follows:

mdio@24520 {
	phy0: ethernet-phy@0 {
		interrupts = &lt;10 1 0 0&gt;;
		reg = &lt;0x0&gt;;
	};
	phy1: ethernet-phy@1 {
		interrupts = &lt;10 1 0 0&gt;;
		reg = &lt;0x1&gt;;
	};
	phy2: ethernet-phy@2 {
		interrupts = &lt;10 1 0 0&gt;;
		reg = &lt;0x2&gt;;
	};
	phy3: ethernet-phy@3 {
		interrupts = &lt;10 1 0 0&gt;;
		reg = &lt;0x3&gt;;
	};

	tbi0: tbi-phy@11 {
		reg = &lt;0x11&gt;;
		device_type = "tbi-phy";
	};
};

Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Jia Hongtao &lt;B38951@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The issue log on core1 is:
root@mpc8572ds:~# ifconfig eth0 10.192.208.244
net eth0: could not attach to PHY
SIOCSIFFLAGS: No such device

To attach PHY node mdio@24520 should not be disabled in dts of core1.
Because all PHYs are controlled through this node as follows:

mdio@24520 {
	phy0: ethernet-phy@0 {
		interrupts = &lt;10 1 0 0&gt;;
		reg = &lt;0x0&gt;;
	};
	phy1: ethernet-phy@1 {
		interrupts = &lt;10 1 0 0&gt;;
		reg = &lt;0x1&gt;;
	};
	phy2: ethernet-phy@2 {
		interrupts = &lt;10 1 0 0&gt;;
		reg = &lt;0x2&gt;;
	};
	phy3: ethernet-phy@3 {
		interrupts = &lt;10 1 0 0&gt;;
		reg = &lt;0x3&gt;;
	};

	tbi0: tbi-phy@11 {
		reg = &lt;0x11&gt;;
		device_type = "tbi-phy";
	};
};

Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Jia Hongtao &lt;B38951@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Add BSC9131 RDB Support</title>
<updated>2012-07-10T12:07:22+00:00</updated>
<author>
<name>Prabhakar Kushwaha</name>
<email>prabhakar@freescale.com</email>
</author>
<published>2012-03-22T04:54:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=d729b900e589e1f20294de1abaef067d6b9b2124'/>
<id>d729b900e589e1f20294de1abaef067d6b9b2124</id>
<content type='text'>
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The
BSC9131 is integrated SoC that targets Femto base station market. It
combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte
    shared L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel
      Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE
      UP/DL Channel processing, and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
      Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix
      Inversion operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit
      with ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network
      acceleration including IEEE 1588. v2 hardware support and
      virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single
      port) and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD
      support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

 BSC9131RDB Overview
 ----------------------
    BSC9131 SoC
    1Gbyte DDR3 (on board DDR)
    128Mbyte 2K page size NAND Flash
    256 Kbit M24256 I2C EEPROM
    128 Mbit SPI Flash memory
    USB-ULPI
    eTSEC1: Connected to RGMII PHY
    eTSEC2: Connected to RGMII PHY
    DUART interface: supports one UARTs up to 115200 bps for console display

 Linux runs on e500v2 core and access some DSP peripherals like AIC

Signed-off-by: Ramneek Mehresh &lt;ramneek.mehresh@freescale.com&gt;
Signed-off-by: Priyanka Jain &lt;Priyanka.Jain@freescale.com&gt;
Signed-off-by: Akhil Goyal &lt;Akhil.Goyal@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Rajan Srivastava &lt;rajan.srivastava@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The
BSC9131 is integrated SoC that targets Femto base station market. It
combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte
    shared L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel
      Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE
      UP/DL Channel processing, and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
      Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix
      Inversion operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit
      with ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network
      acceleration including IEEE 1588. v2 hardware support and
      virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single
      port) and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD
      support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

 BSC9131RDB Overview
 ----------------------
    BSC9131 SoC
    1Gbyte DDR3 (on board DDR)
    128Mbyte 2K page size NAND Flash
    256 Kbit M24256 I2C EEPROM
    128 Mbit SPI Flash memory
    USB-ULPI
    eTSEC1: Connected to RGMII PHY
    eTSEC2: Connected to RGMII PHY
    DUART interface: supports one UARTs up to 115200 bps for console display

 Linux runs on e500v2 core and access some DSP peripherals like AIC

Signed-off-by: Ramneek Mehresh &lt;ramneek.mehresh@freescale.com&gt;
Signed-off-by: Priyanka Jain &lt;Priyanka.Jain@freescale.com&gt;
Signed-off-by: Akhil Goyal &lt;Akhil.Goyal@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Rajan Srivastava &lt;rajan.srivastava@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "powerpc/p3060qds: Add support for P3060QDS board"</title>
<updated>2012-07-10T12:07:22+00:00</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2012-07-05T22:07:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=ab2aba474379f41c7a2627b5aed76e292e6e8c35'/>
<id>ab2aba474379f41c7a2627b5aed76e292e6e8c35</id>
<content type='text'>
This reverts commit 96cc017c5b7ec095ef047d3c1952b6b6bbf98943.

The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This reverts commit 96cc017c5b7ec095ef047d3c1952b6b6bbf98943.

The P3060 was cancelled before it went into production, so there's no point
in supporting it.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
