linux-stable.git/arch/parisc/kernel/cache.c, branch v5.19.2

parisc: Drop pa_swapper_pg_lock spinlock

2022-08-17T13:13:48+00:00

commit 3fbc9a7de0564c55d8a9584c9cd2c9dfe6bd6d43 upstream.

This spinlock was dropped with commit b7795074a046 ("parisc: Optimize
per-pagetable spinlocks") in kernel v5.12.

Remove it to silence a sparse warning.

Signed-off-by: Helge Deller 
Reported-by: kernel test robot 
Cc:  # v5.12+
Signed-off-by: Greg Kroah-Hartman

parisc: Fix flush_anon_page on PA8800/PA8900

2022-06-26T10:23:15+00:00

Anonymous pages are allocated with the shared mappings colouring,
SHM_COLOUR. Since the alias boundary on machines with PA8800 and
PA8900 processors is unknown, flush_user_cache_page() might not
flush all mappings of a shared anonymous page. Flushing the whole
data cache flushes all mappings.

This won't fix all coherency issues with shared mappings but it
seems to work well in practice.  I haven't seen any random memory
faults in almost a month on a rp3440 running as a debian buildd
machine.

There is a small preformance hit.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller 
Cc: stable@vger.kernel.org   # v5.18+

parisc: Don't enforce DMA completion order in cache flushes

2022-05-23T11:44:24+00:00

The only place we need to ensure all outstanding cache coherence
operations are complete is in invalidate_kernel_vmap_range. All
parisc drivers synchronize DMA operations internally and do not
call invalidate_kernel_vmap_range. We only need this for non-coherent
I/O operations.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

parisc: Rewrite cache flush code for PA8800/PA8900

2022-05-17T19:52:47+00:00

Originally, I was convinced that we needed to use tmpalias flushes
everwhere, for both user and kernel flushes. However, when I modified
flush_kernel_dcache_page_addr, to use a tmpalias flush, my c8000
would crash quite early when booting.

The PDC returns alias values of 0 for the icache and dcache. This
indicates that either the alias boundary is greater than 16MB or
equivalent aliasing doesn't work. I modified the tmpalias code to
make it easy to try alternate boundaries. I tried boundaries up to
128MB but still kernel tmpalias flushes didn't work on c8000.

This led me to conclude that tmpalias flushes don't work on PA8800
and PA8900 machines, and that we needed to flush directly using the
virtual address of user and kernel pages. This is likely the major
cause of instability on the c8000 and rp34xx machines.

Flushing user pages requires doing a temporary context switch as we
have to flush pages that don't belong to the current context. Further,
we have to deal with pages that aren't present. If a page isn't
present, the flush instructions fault on every line.

Other code has been rearranged and simplified based on testing. For
example, I introduced a flush_cache_dup_mm routine. flush_cache_mm
and flush_cache_dup_mm differ in that flush_cache_mm calls
purge_cache_pages and flush_cache_dup_mm calls flush_cache_pages.
In some implementations, pdc is more efficient than fdc. Based on
my testing, I don't believe there's any performance benefit on the
c8000.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

Revert "parisc: Increase parisc_cache_flush_threshold setting"

2022-05-08T18:13:36+00:00

This reverts commit a58e9d0984e8dad53f17ec73ae3c1cc7f8d88151.

Triggers segfaults with 32-bit kernels on PA8500 machines.

Signed-off-by: Helge Deller

parisc: Move CPU startup-related functions into .text section

2022-03-29T19:37:12+00:00

If CONFIG_HOTPLUG_CPU is enabled, those functions will be run again
after bootup. So they need to reside in the .text section.

Signed-off-by: Helge Deller

Revert "parisc: Fix invalidate/flush vmap routines"

2022-03-29T14:23:11+00:00

This reverts commit 53d862fac4a09b9c56cca0433fa9de5732fd05a1.

It turned out that flush_kernel_vmap_range() is being called with
interrupts disabled.  There's no way to flush entire cache with
interrupts disabled.

Signed-off-by: Helge Deller

parisc: Fix invalidate/flush vmap routines

2022-03-21T12:30:54+00:00

Cache move-in for virtual accesses is controlled by the TLB.  Thus,
we must generally purge TLB entries before flushing.  The flush routines
must use TLB entries that inhibit cache move-in.

V2: Load physical address prior to flushing TLB.  In flush_cache_page,
flush TLB when flushing and purging.

V3: Don't flush when start equals end.

Signed-off-by: John David Anglin 
Signed-off-by: Helge Deller

parisc: Avoid flushing cache on cache-less machines

2022-03-18T21:59:59+00:00

Avoid flushing caches in __flush_cache_page() and __purge_cache_page()
if the machine hasn't data or instruction caches - as e.g. in qemu.

Signed-off-by: Helge Deller

parisc: Avoid calling SMP cache flush functions on cache-less machines

2022-03-16T21:52:12+00:00

At least the qemu virtual machine does not provide D- and I-caches,
so skip triggering SMP irqs to flush caches on such machines.

Further optimize the caching code by using static branches and making
some functions static.

Signed-off-by: Helge Deller