linux-stable.git/arch/openrisc/include, branch linux-rolling-stable

openrisc: Add full instruction cache invalidate functions

2026-07-24T14:21:03+00:00

commit 1be031de802ba486a7605b52eda825f128b026e2 upstream.

Add functions to invalidate all cache lines which we will use for
static_key patching.

On OpenRISC there is no instruction to invalidate an entire cache so we
loop and invalidate cache lines one by one.  This is not extremely
expensive on OpenRISC as we usually have only a few hundred cache lines.

I considered using the invalidate cache page or range functions.
However, tracking which ranges need invalidation would have been more
expensive than flushing all pages.

Cc: stable@vger.kernel.org
Signed-off-by: Stafford Horne 
Signed-off-by: Greg Kroah-Hartman

uaccess: unify inline vs outline copy_{from,to}_user() selection

2026-07-24T14:19:23+00:00

[ Upstream commit c02be2ad2b88c67c5d7c06b6aa7083b5b40e1077 ]

The kernel allows arches to select between inline and outline
implementations of the copy_{from,to}_user() by defining individual
INLINE_COPY_FROM_USER and INLINE_COPY_TO_USER, correspondingly.  However,
all arches enable or disable them always together.

Without the real use-case for one helper being inlined while the other
outlined, having independent controls is excessive and error prone.

Switch the codebase to the single unified INLINE_COPY_USER control.

Link: https://lore.kernel.org/20260425020857.356850-3-ynorov@nvidia.com
Signed-off-by: Yury Norov 
Tested-by: Alice Ryhl 
Cc: Arnd Bergmann 
Cc: Christophe Leroy (CS GROUP) 
Cc: Mathieu Desnoyers 
Cc: Peter Zijlstra 
Cc: Randy Dunlap 
Cc: Viktor Malik 
Signed-off-by: Andrew Morton 
Stable-dep-of: bd99fcfc6219 ("uaccess: minimize INLINE_COPY_USER-related ifdefery")
Signed-off-by: Sasha Levin

ring-buffer: Flush and stop persistent ring buffer on panic

2026-05-21T12:20:58+00:00

On real hardware, panic and machine reboot may not flush hardware cache
to memory. This means the persistent ring buffer, which relies on a
coherent state of memory, may not have its events written to the buffer
and they may be lost. Moreover, there may be inconsistency with the
counters which are used for validation of the integrity of the
persistent ring buffer which may cause all data to be discarded.

To avoid this issue, stop recording of the ring buffer on panic and
flush the cache of the ring buffer's memory.

Fixes: e645535a954a ("tracing: Add option to use memmapped memory for trace boot instance")
Cc: stable@vger.kernel.org
Cc: Will Deacon 
Cc: Mathieu Desnoyers 
Cc: Ian Rogers 
Link: https://patch.msgid.link/177751969602.2136606.12031934362587643488.stgit@mhiramat.tok.corp.google.com
Signed-off-by: Masami Hiramatsu (Google) 
Acked-by: Catalin Marinas 
Acked-by: Geert Uytterhoeven 
Signed-off-by: Steven Rostedt

arch, mm: consolidate empty_zero_page

2026-04-05T20:53:01+00:00

Reduce 22 declarations of empty_zero_page to 3 and 23 declarations of
ZERO_PAGE() to 4.

Every architecture defines empty_zero_page that way or another, but for the
most of them it is always a page aligned page in BSS and most definitions
of ZERO_PAGE do virt_to_page(empty_zero_page).

Move Linus vetted x86 definition of empty_zero_page and ZERO_PAGE() to the
core MM and drop these definitions in architectures that do not implement
colored zero page (MIPS and s390).

ZERO_PAGE() remains a macro because turning it to a wrapper for a static
inline causes severe pain in header dependencies.

For the most part the change is mechanical, with these being noteworthy:

* alpha: aliased empty_zero_page with ZERO_PGE that was also used for boot
  parameters. Switching to a generic empty_zero_page removes the aliasing
  and keeps ZERO_PGE for boot parameters only
* arm64: uses __pa_symbol() in ZERO_PAGE() so that definition of
  ZERO_PAGE() is kept intact.
* m68k/parisc/um: allocated empty_zero_page from memblock,
  although they do not support zero page coloring and having it in BSS
  will work fine.
* sparc64 can have empty_zero_page in BSS rather allocate it, but it
  can't use virt_to_page() for BSS. Keep it's definition of ZERO_PAGE()
  but instead of allocating it, make mem_map_zero point to
  empty_zero_page.
* sh: used empty_zero_page for boot parameters at the very early boot.
  Rename the parameters page to boot_params_page and let sh use the generic
  empty_zero_page.
* hexagon: had an amusing comment about empty_zero_page

	/* A handy thing to have if one has the RAM. Declared in head.S */

  that unfortunately had to go :)

Link: https://lkml.kernel.org/r/20260211103141.3215197-4-rppt@kernel.org
Signed-off-by: Mike Rapoport (Microsoft) 
Acked-by: Helge Deller 		[parisc]
Tested-by: Helge Deller 		[parisc]
Reviewed-by: Christophe Leroy (CS GROUP) 
Acked-by: Dave Hansen 
Acked-by: Catalin Marinas 
Acked-by: Magnus Lindholm 	[alpha]
Acked-by: Dinh Nguyen 	[nios2]
Acked-by: Andreas Larsson 	[sparc]
Acked-by: David Hildenbrand (Arm) 
Acked-by: Liam R. Howlett 
Cc: "Borislav Petkov (AMD)" 
Cc: David S. Miller 
Cc: Geert Uytterhoeven 
Cc: Guo Ren 
Cc: Huacai Chen 
Cc: Ingo Molnar 
Cc: Johannes Berg 
Cc: John Paul Adrian Glaubitz 
Cc: Lorenzo Stoakes 
Cc: Madhavan Srinivasan 
Cc: Matt Turner 
Cc: Max Filippov 
Cc: Michael Ellerman 
Cc: Michal Hocko 
Cc: Michal Simek 
Cc: Palmer Dabbelt 
Cc: Richard Weinberger 
Cc: Russell King 
Cc: Stafford Horne 
Cc: Suren Baghdasaryan 
Cc: Vineet Gupta 
Cc: Vlastimil Babka 
Cc: Will Deacon 
Signed-off-by: Andrew Morton

Merge tag 'for-linus' of https://github.com/openrisc/linux

2026-02-12T22:04:43+00:00

Pull OpenRISC updates from Stafford Horne:
 "The main focus for this series has been to improve OpenRISC kernel
  out-of-the-box support for FPGA dev boards.

   - Add device tree configurations for De0 Nano single and multicore
     configurations

   - Fix bug in OpenRISC SMP preventing the kernel from running on FPGA
     boards, due to IPIs not being unmasked on secondary CPUs in some
     configurations

   - Pick up a fix from Brian Masney defining the nop() macro to fix
     build failures on OpenRISC for drivers using it"

* tag 'for-linus' of https://github.com/openrisc/linux:
  openrisc: define arch-specific version of nop()
  openrisc: dts: Add de0 nano multicore config and devicetree
  openrisc: dts: Split simple smp dts to dts and dtsi
  openrisc: Fix IPIs on simple multicore systems
  openrisc: dts: Add de0 nano config and devicetree

treewide: provide a generic clear_user_page() variant

2026-01-21T03:24:39+00:00

Patch series "mm: folio_zero_user: clear page ranges", v11.

This series adds clearing of contiguous page ranges for hugepages.

The series improves on the current discontiguous clearing approach in two
ways:

  - clear pages in a contiguous fashion.
  - use batched clearing via clear_pages() wherever exposed.

The first is useful because it allows us to make much better use of
hardware prefetchers.

The second, enables advertising the real extent to the processor.  Where
specific instructions support it (ex.  string instructions on x86; "mops"
on arm64 etc), a processor can optimize based on this because, instead of
seeing a sequence of 8-byte stores, or a sequence of 4KB pages, it sees a
larger unit being operated on.

For instance, AMD Zen uarchs (for extents larger than LLC-size) switch to
a mode where they start eliding cacheline allocation.  This is helpful not
just because it results in higher bandwidth, but also because now the
cache is not evicting useful cachelines and replacing them with zeroes.

Demand faulting a 64GB region shows performance improvement:

 $ perf bench mem mmap -p $pg-sz -f demand -s 64GB -l 5

                       baseline              +series
                   (GBps +- %stdev)      (GBps +- %stdev)

   pg-sz=2MB       11.76 +- 1.10%        25.34 +- 1.18% [*]   +115.47%  	preempt=*

   pg-sz=1GB       24.85 +- 2.41%        39.22 +- 2.32%       + 57.82%  	preempt=none|voluntary
   pg-sz=1GB         (similar)           52.73 +- 0.20% [#]   +112.19%  	preempt=full|lazy

 [*] This improvement is because switching to sequential clearing
  allows the hardware prefetchers to do a much better job.

 [#] For pg-sz=1GB a large part of the improvement is because of the
  cacheline elision mentioned above. preempt=full|lazy improves upon
  that because, not needing explicit invocations of cond_resched() to
  ensure reasonable preemption latency, it can clear the full extent
  as a single unit. In comparison the maximum extent used for
  preempt=none|voluntary is PROCESS_PAGES_NON_PREEMPT_BATCH (32MB).

  When provided the full extent the processor forgoes allocating
  cachelines on this path almost entirely.

  (The hope is that eventually, in the fullness of time, the lazy
   preemption model will be able to do the same job that none or
   voluntary models are used for, allowing us to do away with
   cond_resched().)

Raghavendra also tested previous version of the series on AMD Genoa and
sees similar improvement [1] with preempt=lazy.

  $ perf bench mem map -p $page-size -f populate -s 64GB -l 10

                    base               patched              change
   pg-sz=2MB       12.731939 GB/sec    26.304263 GB/sec     106.6%
   pg-sz=1GB       26.232423 GB/sec    61.174836 GB/sec     133.2%


This patch (of 8):

Let's drop all variants that effectively map to clear_page() and provide
it in a generic variant instead.

We'll use the macro clear_user_page to indicate whether an architecture
provides it's own variant.

Also, clear_user_page() is only called from the generic variant of
clear_user_highpage(), so define it only if the architecture does not
provide a clear_user_highpage().  And, for simplicity define it in
linux/highmem.h.

Note that for parisc, clear_page() and clear_user_page() map to
clear_page_asm(), so we can just get rid of the custom clear_user_page()
implementation.  There is a clear_user_page_asm() function on parisc, that
seems to be unused.  Not sure what's up with that.

Link: https://lkml.kernel.org/r/20260107072009.1615991-1-ankur.a.arora@oracle.com
Link: https://lkml.kernel.org/r/20260107072009.1615991-2-ankur.a.arora@oracle.com
Signed-off-by: David Hildenbrand 
Co-developed-by: Ankur Arora 
Signed-off-by: Ankur Arora 
Cc: Andy Lutomirski 
Cc: Ankur Arora 
Cc: "Borislav Petkov (AMD)" 
Cc: Boris Ostrovsky 
Cc: David Hildenbrand 
Cc: "H. Peter Anvin" 
Cc: Ingo Molnar 
Cc: Konrad Rzessutek Wilk 
Cc: Lance Yang 
Cc: "Liam R. Howlett" 
Cc: Li Zhe 
Cc: Lorenzo Stoakes 
Cc: Mateusz Guzik 
Cc: Matthew Wilcox (Oracle) 
Cc: Michal Hocko 
Cc: Mike Rapoport 
Cc: Peter Zijlstra 
Cc: Raghavendra K T 
Cc: Suren Baghdasaryan 
Cc: Thomas Gleixner 
Cc: Vlastimil Babka 
Signed-off-by: Andrew Morton

openrisc: define arch-specific version of nop()

2026-01-20T19:24:05+00:00

When compiling a driver written for MIPS on OpenRISC that uses the nop()
function, it fails due to the following error:

    drivers/watchdog/pic32-wdt.c: Assembler messages:
    drivers/watchdog/pic32-wdt.c:125: Error: unrecognized instruction `nop'

The driver currently uses the generic version of nop() from
include/asm-generic/barrier.h:

    #ifndef nop
    #define nop()   asm volatile ("nop")
    #endif

Let's fix this on OpenRISC by defining an architecture-specific version
of nop().

This was tested by performing an allmodconfig openrisc cross compile on
an aarch64 host.

Reported-by: kernel test robot 
Closes: https://lore.kernel.org/oe-kbuild-all/202601180236.BVy480We-lkp@intel.com/
Signed-off-by: Brian Masney 
Signed-off-by: Stafford Horne

openrisc: Fix IPIs on simple multicore systems

2026-01-16T16:38:56+00:00

Commit c05671846451 ("openrisc: sleep instead of spin on secondary
wait") fixed OpenRISC SMP Linux for QEMU. However, stability was never
achieved on FPGA development boards.  This is because the above patch
has a step to unmask IPIs on non-boot cpu's but on hardware without
power management, IPIs remain masked.

This meant that IPI's were never actually working on the simple SMP
systems we run on development boards.  The systems booted but stability
was very suspect.

Add the ability to unmask IPI's on the non-boot cores.  This is done by
making the OMPIC IRQs proper percpu IRQs.  We can then use the
enabled_percpu_irq() to unmask IRQ on the non-boot cpus.

Update the or1k PIC driver to use a flow handler that can switch between
percpu and the configured level or edge flow handlers at runtime.
This mechanism is inspired by that done in the J-Core AIC driver.

Signed-off-by: Stafford Horne 
Acked-by: Thomas Gleixner

Merge tag 'for-linus' of https://github.com/openrisc/linux

2025-10-05T17:02:54+00:00

Pull OpenRISC updates from Stafford Horne:
 "I picked up one series from Chen Miao, our Google Summer of Code
  contributor, which adds OpenRISC support for static keys"

* tag 'for-linus' of https://github.com/openrisc/linux:
  openrisc: Add jump label support
  openrisc: Regenerate defconfigs.
  openrisc: Add R_OR1K_32_PCREL relocation type module support
  openrisc: Add text patching API support

Merge tag 'pull-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

2025-10-03T18:37:50+00:00

Pull misc non-vfs updates from Al Viro:
 "Assorted dead code removal around asm/pgtable.h"

* tag 'pull-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
  alpha: unobfuscate _PAGE_P() definition
  kill FIRST_USER_PGD_NR
  alpha: get rid of the remnants of BAD_PAGE and friends
  SET_PAGE_DIR() users had been gone since 2.3.12pre1
  PAGE_PTR() had been last used outside of arch/* in 1.1.94
  csky: remove BS check for FAULT_FLAG_ALLOW_RETRY