linux-stable.git/arch/nds32/kernel/head.S, branch linux-5.2.y Linux kernel stable tree treewide: replace #include <asm/sizes.h> with #include <linux/sizes.h> 2019-05-15T02:52:52+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2019-05-14T22:46:51+00:00 87dfb311b707cd4c4b666c9af0fa15acbe6eee99 Since commit dccd2304cc90 ("ARM: 7430/1: sizes.h: move from asm-generic to <linux/sizes.h>"), <asm/sizes.h> and <asm-generic/sizes.h> are just wrappers of <linux/sizes.h>. This commit replaces all <asm/sizes.h> and <asm-generic/sizes.h> to prepare for the removal. Link: http://lkml.kernel.org/r/1553267665-27228-1-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> 
Since commit dccd2304cc90 ("ARM: 7430/1: sizes.h: move from asm-generic
to <linux/sizes.h>"), <asm/sizes.h> and <asm-generic/sizes.h> are just
wrappers of <linux/sizes.h>.

This commit replaces all <asm/sizes.h> and <asm-generic/sizes.h> to
prepare for the removal.

Link: http://lkml.kernel.org/r/1553267665-27228-1-git-send-email-yamada.masahiro@socionext.com
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
nds32: support hardware prefetcher 2018-11-22T10:13:51+00:00 Nylon Chen nylon7@andestech.com 2018-11-08T11:28:15+00:00 e2f3f8b4a497d26bdcd55a53246ec2e613ae0fd4 We add a config for user to enable or disable this feature. It can be used to control the hardware prefetch function. Signed-off-by: Nylon Chen <nylon7@andestech.com> Acked-by: Greentime Hu <greentime@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> 
We add a config for user to enable or disable this feature.
It can be used to control the hardware prefetch function.

Signed-off-by: Nylon Chen <nylon7@andestech.com>
Acked-by: Greentime Hu <greentime@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
nds32: Fill all TLB entries with kernel image mapping 2018-11-06T10:01:39+00:00 Zong Li zongbox@gmail.com 2018-10-17T13:15:52+00:00 8730c178b4208ec52f4c2b381d9a2b685a791b1c We use earlycon replace with early_printk and doesn't use early_io_map() to create UART mapping. It is not necessary to reserve the one way in TLB for now. It didn't make sense if use direct-mapped and reserve one way at the same time. It allow the direct-mapped now. Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> 
We use earlycon replace with early_printk and doesn't use
early_io_map() to create UART mapping. It is not necessary
to reserve the one way in TLB for now.

It didn't make sense if use direct-mapped and reserve one
way at the same time. It allow the direct-mapped now.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
nds32: Remove the redundant assignment 2018-11-06T10:01:38+00:00 Zong Li zongbox@gmail.com 2018-10-17T13:15:51+00:00 2e95c4d672ce6c931951c87b5dbfa4106fd3cae6 For early version, the value of r2 register was used to display a character on UART when error occurred. Remove these r2 assignments because we no longer show the character. Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> 
For early version, the value of r2 register was used to display
a character on UART when error occurred. Remove these r2 assignments
because we no longer show the character.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
nds32: To fix a cache inconsistency issue by setting correct cacheability of NTC 2018-05-23T05:26:22+00:00 Greentime Hu greentime@andestech.com 2018-04-30T07:02:27+00:00 abb90a24eade1f612324de0e6920041ef64795cb The nds32 architecture will use physical memory when interrupt or exception comes and it will use the setting of NTC0-4. The original implementation didn't consider the DRAM start address may start from 1GB, 2GB or 3GB to cause this issue. It will write the data to DRAM if it is running in physical address however kernel will read the data with virtaul address through data cache. In this case, the data of DRAM is latest. This fix will set the correct cacheability to let kernel write/read the latest data in cache instead of DRAM. Signed-off-by: Greentime Hu <greentime@andestech.com> 
The nds32 architecture will use physical memory when interrupt or
exception comes and it will use the setting of NTC0-4. The original
implementation didn't consider the DRAM start address may start from 1GB,
2GB or 3GB to cause this issue. It will write the data to DRAM if it is
running in physical address however kernel will read the data with
virtaul address through data cache. In this case, the data of DRAM is
latest.

This fix will set the correct cacheability to let kernel write/read the
latest data in cache instead of DRAM.

Signed-off-by: Greentime Hu <greentime@andestech.com>
nds32: Kernel booting and initialization 2018-02-22T02:44:31+00:00 Greentime Hu greentime@andestech.com 2017-10-24T06:33:30+00:00 001d953ede35dfb135e636af4b41d5dd20a09471 This patch includes the kernel startup code. It can get dtb pointer passed from bootloader. It will create a temp mapping by tlb instructions at beginning and goto start_kernel. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> Acked-by: Arnd Bergmann <arnd@arndb.de> 
This patch includes the kernel startup code. It can get dtb pointer
passed from bootloader. It will create a temp mapping by tlb
instructions at beginning and goto start_kernel.

Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>