<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/arch/mips, branch v3.11.2</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>MIPS: ath79: Fix ar933x watchdog clock</title>
<updated>2013-09-27T00:21:56+00:00</updated>
<author>
<name>Felix Fietkau</name>
<email>nbd@openwrt.org</email>
</author>
<published>2013-08-28T08:41:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=2e7120add8f30650e99ab397bd03de2d4b8c1b35'/>
<id>2e7120add8f30650e99ab397bd03de2d4b8c1b35</id>
<content type='text'>
commit a1191927ace7e6f827132aa9e062779eb3f11fa5 upstream.

The watchdog device on the AR933x is connected to
the AHB clock, however the current code uses the
reference clock. Due to the wrong rate, the watchdog
driver can't calculate correct register values for
a given timeout value and the watchdog unexpectedly
restarts the system.

The code uses the wrong value since the initial
commit 04225e1d227c8e68d685936ecf42ac175fec0e54
(MIPS: ath79: add AR933X specific clock init)

The patch fixes the code to use the correct clock
rate to avoid the problem.

Signed-off-by: Felix Fietkau &lt;nbd@openwrt.org&gt;
Signed-off-by: Gabor Juhos &lt;juhosg@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5777/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit a1191927ace7e6f827132aa9e062779eb3f11fa5 upstream.

The watchdog device on the AR933x is connected to
the AHB clock, however the current code uses the
reference clock. Due to the wrong rate, the watchdog
driver can't calculate correct register values for
a given timeout value and the watchdog unexpectedly
restarts the system.

The code uses the wrong value since the initial
commit 04225e1d227c8e68d685936ecf42ac175fec0e54
(MIPS: ath79: add AR933X specific clock init)

The patch fixes the code to use the correct clock
rate to avoid the problem.

Signed-off-by: Felix Fietkau &lt;nbd@openwrt.org&gt;
Signed-off-by: Gabor Juhos &lt;juhosg@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5777/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Handle OCTEON BBIT instructions in FPU emulator.</title>
<updated>2013-08-20T17:17:40+00:00</updated>
<author>
<name>David Daney</name>
<email>david.daney@cavium.com</email>
</author>
<published>2013-08-19T19:10:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=c26d421987d5595ef1758d42dbce02308d10e17e'/>
<id>c26d421987d5595ef1758d42dbce02308d10e17e</id>
<content type='text'>
The branch emulation needs to handle the OCTEON BBIT instructions,
otherwise we get SIGILL instead of emulation.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5726/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The branch emulation needs to handle the OCTEON BBIT instructions,
otherwise we get SIGILL instead of emulation.

Signed-off-by: David Daney &lt;david.daney@cavium.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5726/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: BMIPS: fix hardware interrupt routing for boot CPU != 0</title>
<updated>2013-08-05T11:35:18+00:00</updated>
<author>
<name>Florian Fainelli</name>
<email>florian@openwrt.org</email>
</author>
<published>2013-08-05T10:50:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=fcfa66de8a2f0631a65a2cec0f6149dafd36ec81'/>
<id>fcfa66de8a2f0631a65a2cec0f6149dafd36ec81</id>
<content type='text'>
The hardware interrupt routing for boot CPU != 0 is wrong because it
will route all the hardware interrupts to TP0 which is not the one we
booted from. Fix this by properly checking which boot CPU we are booting
from and updating the right interrupt mask for the boot CPU. This fixes
booting on BCM3368 with bmips_smp_emabled = 0.

Signed-off-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: jogo@openwrt.org
Cc: cernekee@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/5650/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The hardware interrupt routing for boot CPU != 0 is wrong because it
will route all the hardware interrupts to TP0 which is not the one we
booted from. Fix this by properly checking which boot CPU we are booting
from and updating the right interrupt mask for the boot CPU. This fixes
booting on BCM3368 with bmips_smp_emabled = 0.

Signed-off-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Cc: jogo@openwrt.org
Cc: cernekee@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/5650/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: oprofile: Fix BUG due to smp_processor_id() in preemptible code.</title>
<updated>2013-08-05T11:34:22+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2013-08-01T16:31:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=cf5b2d23a75cbb53785d270e76e4911e84797b72'/>
<id>cf5b2d23a75cbb53785d270e76e4911e84797b72</id>
<content type='text'>
current_cpu_type() is not preemption-safe.
If CONFIG_PREEMPT is enabled then mipsxx_reg_setup() can be called from preemptible state.
Added get_cpu()/put_cpu() pair to make it preemption-safe.

This was found while testing oprofile with CONFIG_DEBUG_PREEMPT enable.

/usr/zntestsuite # opcontrol --init
/usr/zntestsuite # opcontrol --setup --event=L2_CACHE_ACCESSES:500 --event=L2_CACHE_MISSES:500 --no-vmlinux
/usr/zntestsuite # opcontrol --start
Using 2.6+ OProfile kernel interface.
BUG: using smp_processor_id() in preemptible [00000000] code: oprofiled/1362
caller is mipsxx_reg_setup+0x11c/0x164
CPU: 0 PID: 1362 Comm: oprofiled Not tainted 3.10.4 #18
Stack : 00000006 70757465 00000000 00000000 00000000 00000000 80b173f6 00000037
          80b10000 00000000 80b21614 88f5a220 00000000 00000000 00000000 00000000
          00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
          00000000 00000000 00000000 89c49c00 89c49c2c 80721254 807b7927 8012c1d0
          80b10000 80721254 00000000 00000552 88f5a220 80b1335c 807b78e6 89c49ba8
          ...
Call Trace:
[&lt;801099a4&gt;] show_stack+0x64/0x7c
[&lt;80665520&gt;] dump_stack+0x20/0x2c
[&lt;803a2250&gt;] debug_smp_processor_id+0xe0/0xf0
[&lt;8052df24&gt;] mipsxx_reg_setup+0x11c/0x164
[&lt;8052cd70&gt;] op_mips_setup+0x24/0x4c
[&lt;80529cfc&gt;] oprofile_setup+0x5c/0x12c
[&lt;8052b9f8&gt;] event_buffer_open+0x78/0xf8
[&lt;801c3150&gt;] do_dentry_open.isra.15+0x2b8/0x3b0
[&lt;801c3270&gt;] finish_open+0x28/0x4c
[&lt;801d49b8&gt;] do_last.isra.41+0x2cc/0xd00
[&lt;801d54a0&gt;] path_openat+0xb4/0x4c4
[&lt;801d5c44&gt;] do_filp_open+0x3c/0xac
[&lt;801c4744&gt;] do_sys_open+0x110/0x1f4
[&lt;8010f47c&gt;] stack_done+0x20/0x44

Bug reported and original patch by Jerin Jacob &lt;jerinjacobk@gmail.com&gt;.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Acked-by: Jerin Jacob &lt;jerinjacobk@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
current_cpu_type() is not preemption-safe.
If CONFIG_PREEMPT is enabled then mipsxx_reg_setup() can be called from preemptible state.
Added get_cpu()/put_cpu() pair to make it preemption-safe.

This was found while testing oprofile with CONFIG_DEBUG_PREEMPT enable.

/usr/zntestsuite # opcontrol --init
/usr/zntestsuite # opcontrol --setup --event=L2_CACHE_ACCESSES:500 --event=L2_CACHE_MISSES:500 --no-vmlinux
/usr/zntestsuite # opcontrol --start
Using 2.6+ OProfile kernel interface.
BUG: using smp_processor_id() in preemptible [00000000] code: oprofiled/1362
caller is mipsxx_reg_setup+0x11c/0x164
CPU: 0 PID: 1362 Comm: oprofiled Not tainted 3.10.4 #18
Stack : 00000006 70757465 00000000 00000000 00000000 00000000 80b173f6 00000037
          80b10000 00000000 80b21614 88f5a220 00000000 00000000 00000000 00000000
          00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
          00000000 00000000 00000000 89c49c00 89c49c2c 80721254 807b7927 8012c1d0
          80b10000 80721254 00000000 00000552 88f5a220 80b1335c 807b78e6 89c49ba8
          ...
Call Trace:
[&lt;801099a4&gt;] show_stack+0x64/0x7c
[&lt;80665520&gt;] dump_stack+0x20/0x2c
[&lt;803a2250&gt;] debug_smp_processor_id+0xe0/0xf0
[&lt;8052df24&gt;] mipsxx_reg_setup+0x11c/0x164
[&lt;8052cd70&gt;] op_mips_setup+0x24/0x4c
[&lt;80529cfc&gt;] oprofile_setup+0x5c/0x12c
[&lt;8052b9f8&gt;] event_buffer_open+0x78/0xf8
[&lt;801c3150&gt;] do_dentry_open.isra.15+0x2b8/0x3b0
[&lt;801c3270&gt;] finish_open+0x28/0x4c
[&lt;801d49b8&gt;] do_last.isra.41+0x2cc/0xd00
[&lt;801d54a0&gt;] path_openat+0xb4/0x4c4
[&lt;801d5c44&gt;] do_filp_open+0x3c/0xac
[&lt;801c4744&gt;] do_sys_open+0x110/0x1f4
[&lt;8010f47c&gt;] stack_done+0x20/0x44

Bug reported and original patch by Jerin Jacob &lt;jerinjacobk@gmail.com&gt;.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Acked-by: Jerin Jacob &lt;jerinjacobk@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: PNX833x: PNX8335_PCI_ETHERNET_INT depends on CONFIG_SOC_PNX8335</title>
<updated>2013-08-05T11:34:22+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2013-07-09T08:21:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=3ac3bcb9625dad4074cb67a8e319ea369d61dcdb'/>
<id>3ac3bcb9625dad4074cb67a8e319ea369d61dcdb</id>
<content type='text'>
The PNX8335_PCI_ETHERNET_INT macro is defined in
arch/mips/include/asm/mach-pnx833x/irq-mapping.h
only if CONFIG_SOC_PNX8335 is selected.

Fixes the following randconfig problem:
arch/mips/pnx833x/common/platform.c:210:12:
error: 'PNX8335_PIC_ETHERNET_INT' undeclared here
(not in a function)

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Acked-by: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5585/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The PNX8335_PCI_ETHERNET_INT macro is defined in
arch/mips/include/asm/mach-pnx833x/irq-mapping.h
only if CONFIG_SOC_PNX8335 is selected.

Fixes the following randconfig problem:
arch/mips/pnx833x/common/platform.c:210:12:
error: 'PNX8335_PIC_ETHERNET_INT' undeclared here
(not in a function)

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Acked-by: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5585/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: BMIPS: fix slave CPU booting when physical CPU is not 0</title>
<updated>2013-07-30T16:54:29+00:00</updated>
<author>
<name>Florian Fainelli</name>
<email>florian@openwrt.org</email>
</author>
<published>2013-07-24T16:12:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=ff5fadaff39180dc0b652753b5614a564711be29'/>
<id>ff5fadaff39180dc0b652753b5614a564711be29</id>
<content type='text'>
The current BMIPS SMP code assumes that the slave CPU is physical and
logical CPU 1, but on some systems such as BCM3368, the slave CPU is
physical CPU0. Fix the code to read the physical CPU (thread ID) we are
running this code on, and adjust the relocation vector address based on
it. This allows bringing up the second CPU on BCM3368 for instance.

Signed-off-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Cc: blogic@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/5621/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The current BMIPS SMP code assumes that the slave CPU is physical and
logical CPU 1, but on some systems such as BCM3368, the slave CPU is
physical CPU0. Fix the code to read the physical CPU (thread ID) we are
running this code on, and adjust the relocation vector address based on
it. This allows bringing up the second CPU on BCM3368 for instance.

Signed-off-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Cc: blogic@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/5621/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: BMIPS: do not change interrupt routing depending on boot CPU</title>
<updated>2013-07-30T16:54:09+00:00</updated>
<author>
<name>Florian Fainelli</name>
<email>florian@openwrt.org</email>
</author>
<published>2013-07-24T16:12:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=c4091d3fbbed922a3641e5e749655e49cc0d4dee'/>
<id>c4091d3fbbed922a3641e5e749655e49cc0d4dee</id>
<content type='text'>
Commit 4df715aa ("MIPS: BMIPS: support booting from physical CPU other
than 0") changed the interupt routing when we are booting from physical
CPU 0, but the settings are actually correct if we are booting from
physical CPU 0 or CPU 1. Revert that specific change.

Signed-off-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Cc: blogic@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/5622/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit 4df715aa ("MIPS: BMIPS: support booting from physical CPU other
than 0") changed the interupt routing when we are booting from physical
CPU 0, but the settings are actually correct if we are booting from
physical CPU 0 or CPU 1. Revert that specific change.

Signed-off-by: Florian Fainelli &lt;florian@openwrt.org&gt;
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Cc: blogic@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/5622/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: powertv: Fix arguments for free_reserved_area()</title>
<updated>2013-07-30T16:50:31+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2013-07-25T15:11:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=c055629b279d68c79b8776681c17a2234fecf8af'/>
<id>c055629b279d68c79b8776681c17a2234fecf8af</id>
<content type='text'>
Commit 6e7582bf35b8a5a330fd08b398ae445bac86917a
"MIPS: PowerTV: use free_reserved_area() to simplify code"

merged in 3.11-rc1, broke the build for the powertv defconfig with
the following build error:

arch/mips/powertv/asic/asic_devices.c: In function 'platform_release_memory':
arch/mips/powertv/asic/asic_devices.c:533:7: error: passing argument 1 of
'free_reserved_area' makes pointer from integer without a cast [-Werror]

The free_reserved_area() function expects a void * pointer for the start
address and a void * pointer for the end one.

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5624/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit 6e7582bf35b8a5a330fd08b398ae445bac86917a
"MIPS: PowerTV: use free_reserved_area() to simplify code"

merged in 3.11-rc1, broke the build for the powertv defconfig with
the following build error:

arch/mips/powertv/asic/asic_devices.c: In function 'platform_release_memory':
arch/mips/powertv/asic/asic_devices.c:533:7: error: passing argument 1 of
'free_reserved_area' makes pointer from integer without a cast [-Werror]

The free_reserved_area() function expects a void * pointer for the start
address and a void * pointer for the end one.

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5624/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: Set default CPU type for BCM47XX platforms</title>
<updated>2013-07-30T16:48:50+00:00</updated>
<author>
<name>Markos Chandras</name>
<email>markos.chandras@imgtec.com</email>
</author>
<published>2013-07-23T14:40:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=314878d246955e0c6fff95d8ae64285fe828c785'/>
<id>314878d246955e0c6fff95d8ae64285fe828c785</id>
<content type='text'>
If neither BCM47XX_SSD nor BCM47XX_BCMA is selected, then no
CPU type is available leading to build problems. We fix
this problem by using MIPS32r1 as the default CPU type for
the BCM47XX platform.

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Acked-by: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5618/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If neither BCM47XX_SSD nor BCM47XX_BCMA is selected, then no
CPU type is available leading to build problems. We fix
this problem by using MIPS32r1 as the default CPU type for
the BCM47XX platform.

Signed-off-by: Markos Chandras &lt;markos.chandras@imgtec.com&gt;
Acked-by: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5618/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>MIPS: uapi/asm/siginfo.h: Fix GCC 4.1.2 compilation</title>
<updated>2013-07-30T16:40:40+00:00</updated>
<author>
<name>Maciej W. Rozycki</name>
<email>macro@linux-mips.org</email>
</author>
<published>2013-07-28T20:20:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=1d3e2d79a7d5ab56b382ea96b64c4daa9d6f0ce4'/>
<id>1d3e2d79a7d5ab56b382ea96b64c4daa9d6f0ce4</id>
<content type='text'>
It wasn't until GCC 4.3 I believe that the __SIZEOF_*__ predefined macros
were added.  The change below switches &lt;uapi/asm/siginfo.h&gt; to the
_MIPS_SZLONG macro so that compilation with e.g. GCC 4.1.2 succeeds.
This is a user API header so I think this is even more important, for
older userland support.  The change adds an unsuccessful default too, to
catch any compiler configuration oddities.

Signed-off-by: Maciej W. Rozycki &lt;macro@linux-mips.org&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5630/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
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<pre>
It wasn't until GCC 4.3 I believe that the __SIZEOF_*__ predefined macros
were added.  The change below switches &lt;uapi/asm/siginfo.h&gt; to the
_MIPS_SZLONG macro so that compilation with e.g. GCC 4.1.2 succeeds.
This is a user API header so I think this is even more important, for
older userland support.  The change adds an unsuccessful default too, to
catch any compiler configuration oddities.

Signed-off-by: Maciej W. Rozycki &lt;macro@linux-mips.org&gt;
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5630/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
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