linux-stable.git/arch/mips/power, branch linux-3.2.y

MIPS: Hibernate: flush TLB entries earlier

2015-08-06T23:32:02+00:00

commit 2a21dc7c196209d94cb570a0d340faa6c760f7f8 upstream.

We found that TLB mismatch not only happens after kernel resume, but
also happens during snapshot restore. So move it to the beginning of
swsusp_arch_suspend().

Signed-off-by: Huacai Chen 
Cc: Steven J. Hill 
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang 
Cc: Zhangjin Wu 
Patchwork: https://patchwork.linux-mips.org/patch/9621/
Signed-off-by: Ralf Baechle 
Signed-off-by: Ben Hutchings

MIPS: Hibernate: Flush TLB entries in swsusp_arch_resume()

2014-04-30T15:23:24+00:00

commit c14af233fbe279d0e561ecf84f1208b1bae087ef upstream.

The original MIPS hibernate code flushes cache and TLB entries in
swsusp_arch_resume(). But they are removed in Commit 44eeab67416711
(MIPS: Hibernation: Remove SMP TLB and cacheflushing code.). A cross-
CPU flush is surely unnecessary because all but the local CPU have
already been disabled. But a local flush (at least the TLB flush) is
needed. When we do hibernation on Loongson-3 with an E1000E NIC, it is
very easy to produce a kernel panic (kernel page fault, or unaligned
access). The root cause is E1000E driver use vzalloc_node() to allocate
pages, the stale TLB entries of the booting kernel will be misused by
the resumed target kernel.

Signed-off-by: Huacai Chen 
Cc: John Crispin 
Cc: Steven J. Hill 
Cc: Aurelien Jarno 
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang 
Cc: Zhangjin Wu 
Patchwork: https://patchwork.linux-mips.org/patch/6643/
Signed-off-by: Ralf Baechle 
Signed-off-by: Ben Hutchings

MIPS: Hibernation: Fixes for PAGE_SIZE >= 64kb

2011-05-10T17:15:26+00:00

PAGE_SIZE >= 64kb (1 << 16) is too big to be the immediate of the
addiu/daddiu instruction, so, use addu/daddu instruction instead.

The following compiling error is fixed:

AS      arch/mips/power/hibernate.o
arch/mips/power/hibernate.S: Assembler messages:
arch/mips/power/hibernate.S:38: Error: expression out of range
make[2]: *** [arch/mips/power/hibernate.o] Error 1
make[1]: *** [arch/mips/power] Error 2

Reported-by: Roman Mamedov 
Signed-off-by: Wu Zhangjin 
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2313/
Signed-off-by: Ralf Baechle

MIPS: Loongson: Change the Email address of Wu Zhangjin

2010-02-27T11:53:12+00:00

Currently wuzj@lemote.com is not usable; change it to wuzhangjin@gmail.com.

Signed-off-by: Wu Zhangjin 
Cc: linux-mips@linux-mips.org
Cc: yanh@lemote.com
Cc: huhb@lemote.com
Cc: zhangfx@lemote.com
Patchwork: http://patchwork.linux-mips.org/patch/829/
Signed-off-by: Ralf Baechle

MIPS: Use PAGE_SIZE in assembly instead of _PAGE_SIZE.

2009-09-17T18:07:48+00:00

Now that PAGE_SIZE is available to assembly directly, there is no need
to separately expose it as _PAGE_SIZE through asm-offsets.

In addition, remove _PAGE_SHIFT from asm-offsets, since it was never
needed, and is not used anywhere.

Signed-off-by: Nelson Elhage 
Signed-off-by: Tim Abbott 
Signed-off-by: Ralf Baechle

MIPS: Hibernation: Remove SMP TLB and cacheflushing code.

2009-06-24T17:34:39+00:00

We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled.  A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled.  A local
flush is not needed either because we didn't change any mappings.  So
just delete the code.

Signed-off-by: Ralf Baechle

MIPS: Add hibernation support

2009-06-17T10:06:31+00:00

[Ralf: SMP support requires CPU hotplugging which MIPS currently doesn't
support.  As implemented in this patch cache and tlb flushing will also be
invoked with interrupts disabled so smp_call_function() will blow up in
charming ways.  So limit to !SMP.]

Reviewed-by: Pavel Machek 
Reviewed-by: Yan Hua 
Reviewed-by: Arnaud Patard 
Reviewed-by: Atsushi Nemoto 
Signed-off-by: Wu Zhangjin 
Signed-off-by: Hu Hongbing 
Signed-off-by: Ralf Baechle