<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/arch/mips/kernel, branch linux-2.6.22.y</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>[MIPS] Fix scheduling latency issue on 24K, 34K and 74K cores</title>
<updated>2007-07-06T15:17:11+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-06-20T23:22:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=4b3e975e4a06f1710693c5aa51b8f98facfa9863'/>
<id>4b3e975e4a06f1710693c5aa51b8f98facfa9863</id>
<content type='text'>
The idle loop goes to sleep using the WAIT instruction if !need_resched().
This has is suffering from from a race condition that if if just after
need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but
we've just completed the test so go to sleep anyway.  This would be
trivial to fix by just disabling interrupts during that sequence as in:

        local_irq_disable();
        if (!need_resched())
                __asm__("wait");
        local_irq_enable();

but the processor architecture leaves it undefined if a processor calling
WAIT with interrupts disabled will ever restart its pipeline and indeed
some processors have made use of the freedom provided by the architecture
definition.  This has been resolved and the Config7.WII bit indicates that
the use of WAIT is safe on 24K, 24KE and 34K cores.  It also is safe on
74K starting revision 2.1.0 so enable the use of WAIT with interrupts
disabled for 74K based on a c0_prid of at least that.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The idle loop goes to sleep using the WAIT instruction if !need_resched().
This has is suffering from from a race condition that if if just after
need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but
we've just completed the test so go to sleep anyway.  This would be
trivial to fix by just disabling interrupts during that sequence as in:

        local_irq_disable();
        if (!need_resched())
                __asm__("wait");
        local_irq_enable();

but the processor architecture leaves it undefined if a processor calling
WAIT with interrupts disabled will ever restart its pipeline and indeed
some processors have made use of the freedom provided by the architecture
definition.  This has been resolved and the Config7.WII bit indicates that
the use of WAIT is safe on 24K, 24KE and 34K cores.  It also is safe on
74K starting revision 2.1.0 so enable the use of WAIT with interrupts
disabled for 74K based on a c0_prid of at least that.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] Fix timer/performance interrupt detection</title>
<updated>2007-07-06T15:17:11+00:00</updated>
<author>
<name>Chris Dearman</name>
<email>chris@mips.com</email>
</author>
<published>2007-06-21T11:59:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=c3e838a2cbb0f14af4d718160933523ac4c37adf'/>
<id>c3e838a2cbb0f14af4d718160933523ac4c37adf</id>
<content type='text'>
Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] AP/SP: Avoid triggering the 34K E125 performance issue</title>
<updated>2007-07-06T15:17:10+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-06-07T07:44:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=6fb88ce04f545ca7da15a7b447783bb7a4615511'/>
<id>6fb88ce04f545ca7da15a7b447783bb7a4615511</id>
<content type='text'>
C0_status doesn't need to be initialized at this point anyway; the register
will be initialized later.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
C0_status doesn't need to be initialized at this point anyway; the register
will be initialized later.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] VSMP: Fix initialization ordering bug.</title>
<updated>2007-07-04T14:53:16+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-07-03T16:25:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=8c976e34516c9e134488babbb95af182340370c8'/>
<id>8c976e34516c9e134488babbb95af182340370c8</id>
<content type='text'>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] Count timer interrupts correctly.</title>
<updated>2007-06-26T17:57:34+00:00</updated>
<author>
<name>Chris Dearman</name>
<email>chris@mips.com</email>
</author>
<published>2007-06-21T11:59:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=8e15a0e35fdaf19e1aeb7923571e928bd6123cfd'/>
<id>8e15a0e35fdaf19e1aeb7923571e928bd6123cfd</id>
<content type='text'>
Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] use compat_siginfo in rt_sigframe_n32</title>
<updated>2007-06-26T17:57:33+00:00</updated>
<author>
<name>Pavel Kiryukhin</name>
<email>vksavl@gmail.com</email>
</author>
<published>2007-06-05T09:42:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=a76f3a417a431eaf673323459357d8e684b52c49'/>
<id>a76f3a417a431eaf673323459357d8e684b52c49</id>
<content type='text'>
Signed-off-by: Pavel Kiryukhin &lt;vksavl@gmail.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Pavel Kiryukhin &lt;vksavl@gmail.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] 20K: Handle WAIT related bugs according to errata information</title>
<updated>2007-06-26T17:57:33+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-06-12T12:04:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=c8eae71dc81af15809d87d7aabb94810cea9577d'/>
<id>c8eae71dc81af15809d87d7aabb94810cea9577d</id>
<content type='text'>
We used to avoid the WAIT entirely on the 20K but really only need to do
this on early revs of the 20K.  Without this a 20K was a bit of a
power hog.  Well, in the lower power power hog category ;-)

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
We used to avoid the WAIT entirely on the 20K but really only need to do
this on early revs of the 20K.  Without this a 20K was a bit of a
power hog.  Well, in the lower power power hog category ;-)

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] Don't drag a platform specific header into generic arch code.</title>
<updated>2007-06-20T21:27:10+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-06-20T21:27:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=3b1d4ed5353af04d6aa20be2701727b9cdb2ac61'/>
<id>3b1d4ed5353af04d6aa20be2701727b9cdb2ac61</id>
<content type='text'>
For some platforms it's definitions may conflict.  So that's the one-liner.
The rest is 10 square kilometers of collateral damage fixup this include
used to paper over.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For some platforms it's definitions may conflict.  So that's the one-liner.
The rest is 10 square kilometers of collateral damage fixup this include
used to paper over.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] Separate performance counter interrupts</title>
<updated>2007-06-14T17:25:15+00:00</updated>
<author>
<name>Chris Dearman</name>
<email>chris@mips.com</email>
</author>
<published>2007-05-24T21:24:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=ffe9ee4709cf513fb80e9b7e04d214dd8b76a10d'/>
<id>ffe9ee4709cf513fb80e9b7e04d214dd8b76a10d</id>
<content type='text'>
Support for performance counter overflow interrupt that is on a separate
interrupt from the timer.

Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Support for performance counter overflow interrupt that is on a separate
interrupt from the timer.

Signed-off-by: Chris Dearman &lt;chris@mips.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[MIPS] Fix modpost warnings by making start_secondary __cpuinit</title>
<updated>2007-06-11T17:20:54+00:00</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2007-05-31T15:15:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=4ebd5233f0420f1e383c38f962ec84c4d53fbbad'/>
<id>4ebd5233f0420f1e383c38f962ec84c4d53fbbad</id>
<content type='text'>
WARNING: arch/mips/kernel/built-in.o(.text+0x9a58): Section mismatch: reference to .init.text:cpu_report (between 'start_secondary' and 'smp_prepare_boot_cpu')
WARNING: arch/mips/kernel/built-in.o(.text+0x9a60): Section mismatch: reference to .init.text:per_cpu_trap_init (between 'start_secondary' and 'smp_prepare_boot_cpu')
WARNING: arch/mips/kernel/built-in.o(.text+0x9adc): Section mismatch: reference to .init.text:cpu_probe (between 'start_secondary' and 'smp_prepare_boot_cpu')
mipsel-linux-objcopy -S -O srec --remove-section=.reginfo --remove-section=.mdebug --remove-section=.comment --remove-section=.note --remove-section=.pdr --remove-section=.options --remove-section=.MIPS.options vmlinux arch/mips/boot/vmlinux.srec

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
WARNING: arch/mips/kernel/built-in.o(.text+0x9a58): Section mismatch: reference to .init.text:cpu_report (between 'start_secondary' and 'smp_prepare_boot_cpu')
WARNING: arch/mips/kernel/built-in.o(.text+0x9a60): Section mismatch: reference to .init.text:per_cpu_trap_init (between 'start_secondary' and 'smp_prepare_boot_cpu')
WARNING: arch/mips/kernel/built-in.o(.text+0x9adc): Section mismatch: reference to .init.text:cpu_probe (between 'start_secondary' and 'smp_prepare_boot_cpu')
mipsel-linux-objcopy -S -O srec --remove-section=.reginfo --remove-section=.mdebug --remove-section=.comment --remove-section=.note --remove-section=.pdr --remove-section=.options --remove-section=.MIPS.options vmlinux arch/mips/boot/vmlinux.srec

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
