linux-stable.git/arch/mips/kernel/spram.c, branch linux-rolling-stable

MIPS: kernel: Rename read/write_c0_ecc to read/writec0_errctl

2025-01-11T11:31:21+00:00

CP0 register 26 is used as ECC register for legacy cores, but newer
cores (MIPS32/MIPS64) use it as an ErrCtl register. Since the kernel only
uses CP0 26 as ErrCtl register rename the access functions to the more
fitting name.

Signed-off-by: Thomas Bogendoerfer 
Reviewed-by: Maciej W. Rozycki 
Signed-off-by: Thomas Bogendoerfer

mips: spram: fix missing prototype warning for spram_config

2023-12-11T01:21:41+00:00

arch/mips/kernel/spram.c:194:6: error: no previous prototype for 'spram_config' [-Werror=missing-prototypes]

Link: https://lkml.kernel.org/r/20231204115710.2247097-15-arnd@kernel.org
Signed-off-by: Arnd Bergmann 
Cc: Stephen Rothwell 
Cc: Thomas Bogendoerfer 
Signed-off-by: Andrew Morton

mips: Add CONFIG/CONFIG6/Cause reg fields macro

2020-05-22T07:12:22+00:00

There are bit fields which persist in the MIPS CONFIG and CONFIG6
registers, but haven't been described in the generic mipsregs.h
header so far. In particular, the generic CONFIG bitfields are
BE - endian mode, BM - burst mode, SB - SimpleBE, OCP interface mode
indicator, UDI - user-defined "CorExtend" instructions, DSP - data
scratch pad RAM present, ISP - instruction scratch pad RAM present,
etc. The core-specific CONFIG6 bitfields are JRCD - jump register
cache prediction disable, R6 - MIPSr6 extensions enable, IFUPerfCtl -
IFU performance control, SPCD - sleep state performance counter, DLSB -
disable load/store bonding. A new exception code reported in the
ExcCode field of the Cause register: 30 - Parity/ECC error exception
happened on either fetch, load or cache refill. Lets add them to the
mipsregs.h header to be used in future platform code, which have them
utilized.

Signed-off-by: Serge Semin 
Cc: Alexey Malahov 
Cc: Thomas Bogendoerfer 
Cc: Paul Burton 
Cc: Ralf Baechle 
Cc: Arnd Bergmann 
Cc: Rob Herring 
Cc: devicetree@vger.kernel.org
Signed-off-by: Thomas Bogendoerfer

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30T18:26:32+00:00

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman

MIPS: Add P6600 cases to CPU switch statements

2016-05-13T12:01:52+00:00

Add cases supporting the P6600 CPU to various switch statements in
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off-by: Paul Burton 
Cc: Maciej W. Rozycki 
Cc: Peter Zijlstra 
Cc: Joshua Kinard 
Cc: Andrzej Hajda 
Cc: Leonid Yegoshin 
Cc: Paul Gortmaker 
Cc: James Hogan 
Cc: Arnaldo Carvalho de Melo 
Cc: Ingo Molnar 
Cc: Petri Gynther 
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12343/
Signed-off-by: Ralf Baechle

MIPS: Add cases for CPU_I6400

2015-08-26T13:23:03+00:00

Add a CPU_I6400 case to various switch statements, doing the same thing
as for CPU_P5600.

Signed-off-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10635/
Signed-off-by: Ralf Baechle

MIPS: Add cases for CPU_QEMU_GENERIC

2015-02-16T10:01:24+00:00

Add a CPU_QEMU_GENERIC case to various switch statements.

Signed-off-by: Leonid Yegoshin 
Signed-off-by: Markos Chandras

MIPS: Use current_cpu_type() instead of c->cputype

2014-03-31T16:17:12+00:00

If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This
may save about 10k for the compressed kernel image(vmlinuz).

Signed-off-by: Wu Zhangjin 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1901/
Signed-off-by: Ralf Baechle

MIPS: Add cases for CPU_P5600

2014-03-26T22:09:11+00:00

Add a CPU_P5600 case to various switch statements, doing the same thing
as for CPU_PROAPTIV.

Signed-off-by: James Hogan 
Reviewed-by: Markos Chandras 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6408/
Signed-off-by: Ralf Baechle

MIPS: Add 1074K CPU support explicitly.

2014-03-06T20:25:21+00:00

The 1074K is a multiprocessing coherent processing system (CPS) based
on modified 74K cores. This patch makes the 1074K an actual unique
CPU type, instead of a 74K derivative, which it is not.

Signed-off-by: Steven J. Hill 
Reviewed-by: Leonid Yegoshin 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6389/
Signed-off-by: Ralf Baechle