linux-stable.git/arch/mips/kernel/cpu-probe.c, branch v5.15

MIPS: cpu-probe: Fix FPU detection on Ingenic JZ4760(B)

2021-06-01T09:44:47+00:00

Ingenic JZ4760 and JZ4760B do have a FPU, but the config registers don't
report it. Force the FPU detection in case the processor ID match the
JZ4760(B) one.

Signed-off-by: Paul Cercueil 
Signed-off-by: Thomas Bogendoerfer

MIPS: Loongson64: Use _CACHE_UNCACHED instead of _CACHE_UNCACHED_ACCELERATED

2021-04-06T13:12:58+00:00

Loongson64 processors have a writecombine issue that maybe failed to
write back framebuffer used with ATI Radeon or AMD GPU at times, after
commit 8a08e50cee66 ("drm: Permit video-buffers writecombine mapping
for MIPS"), there exists some errors such as blurred screen and lockup,
and so on.

[   60.958721] radeon 0000:03:00.0: ring 0 stalled for more than 10079msec
[   60.965315] radeon 0000:03:00.0: GPU lockup (current fence id 0x0000000000000112 last fence id 0x000000000000011d on ring 0)
[   60.976525] radeon 0000:03:00.0: ring 3 stalled for more than 10086msec
[   60.983156] radeon 0000:03:00.0: GPU lockup (current fence id 0x0000000000000374 last fence id 0x00000000000003a8 on ring 3)

As discussed earlier [1], it might be better to disable writecombine
on the CPU detection side because the root cause is unknown now.

Actually, this patch is a temporary solution to just make it work well,
it is not a proper and final solution, I hope someone will have a better
solution to fix this issue in the future.

[1] https://lore.kernel.org/patchwork/patch/1285542/

Signed-off-by: Tiezhu Yang 
Signed-off-by: Thomas Bogendoerfer

MIPS: kernel: Reserve exception base early to prevent corruption

2021-03-09T10:22:59+00:00

BMIPS is one of the few platforms that do change the exception base.
After commit 2dcb39645441 ("memblock: do not start bottom-up allocations
with kernel_end") we started seeing BMIPS boards fail to boot with the
built-in FDT being corrupted.

Before the cited commit, early allocations would be in the [kernel_end,
RAM_END] range, but after commit they would be within [RAM_START +
PAGE_SIZE, RAM_END].

The custom exception base handler that is installed by
bmips_ebase_setup() done for BMIPS5000 CPUs ends-up trampling on the
memory region allocated by unflatten_and_copy_device_tree() thus
corrupting the FDT used by the kernel.

To fix this, we need to perform an early reservation of the custom
exception space. Additional we reserve the first 4k (1k for R3k) for
either normal exception vector space (legacy CPUs) or special vectors
like cache exceptions.

Huge thanks to Serge for analysing and proposing a solution to this
issue.

Fixes: 2dcb39645441 ("memblock: do not start bottom-up allocations with kernel_end")
Reported-by: Kamal Dasu 
Debugged-by: Serge Semin 
Acked-by: Mike Rapoport 
Tested-by: Florian Fainelli 
Reviewed-by: Serge Semin 
Signed-off-by: Thomas Bogendoerfer

Revert "MIPS: Remove unused R4300 CPU support"

2021-01-22T10:39:45+00:00

This reverts commit f9065b54d437c4660e3d974ad9ce5188c068cd76.

We're adding Nintendo 64 support, so the VR4300 is no longer unused.

Signed-off-by: Lauri Kasanen 
Signed-off-by: Thomas Bogendoerfer

MIPS: Ingenic: Disable HPTLB for D0 XBurst CPUs too

2021-01-18T14:24:02+00:00

The JZ4760 has the HPTLB as well, but has a XBurst CPU with a D0 CPUID.

Disable the HPTLB for all XBurst CPUs with a D0 CPUID. In the case where
there is no HPTLB (e.g. for older SoCs), this won't have any side
effect.

Fixes: b02efeb05699 ("MIPS: Ingenic: Disable abandoned HPTLB function.")
Cc:  # 5.4
Signed-off-by: Paul Cercueil 
Reviewed-by: 周琰杰 (Zhou Yanjie) 
Signed-off-by: Thomas Bogendoerfer

MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bit

2020-10-12T10:05:40+00:00

MIPS_CPU_BP_GHIST is only set two times and more or less immediately
used in cpu-probe.c itself. Remove this option to make room in options
word.

Signed-off-by: Thomas Bogendoerfer

MIPS: cpu-probe: move fpu probing/handling into its own file

2020-10-12T10:04:50+00:00

cpu-probe.c has grown when supporting more and more CPUs and there
are use cases where probing for all the CPUs isn't useful like
running on a R3k system. But still the fpu handling is nearly
the same. For sharing put the fpu code into it's own file.

Signed-off-by: Thomas Bogendoerfer

MIPS: cpu-probe: ingenic: Fix broken BUG_ON

2020-09-18T14:27:32+00:00

The previous code was doing:
BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);

This only worked as the "cpu_has_counter" macro was overridden in
. The default "cpu_has_counter" macro is
non-constant, which triggered the BUG_ON() independently of the value
returned by the macro.

What we want to check here, is that *if* the macro was overridden to a
compile-time constant, then must be defined to zero, otherwise it's a
bug.

So the correct check is:
BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);

Signed-off-by: Paul Cercueil 
Signed-off-by: Thomas Bogendoerfer

MIPS: cpu-probe: Mark XBurst CPU as having vtagged caches

2020-09-18T14:27:00+00:00

XBurst CPUs present in Ingenic SoCs have virtually tagged caches,
according to the  header.

Add that information to cpu_probe_ingenic().

Signed-off-by: Paul Cercueil 
Signed-off-by: Thomas Bogendoerfer

MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA

2020-09-18T14:26:36+00:00

Previously, in cpu_probe_ingenic(), c->writecombine was set to
_CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when
CONFIG_MACH_INGENIC was set. This made it impossible to support multiple
CPUs.

Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA
directly and removing the dependency on CONFIG_MACH_INGENIC.

Signed-off-by: Paul Cercueil 
Signed-off-by: Thomas Bogendoerfer